[PATCH] drm/xe: use xe_mmio_read32() to read mtcfg register

[Upadhyay, Tejas]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of
> Shuicheng Lin
> Sent: 13 May 2025 09:25
> To: intel-xe at lists.freedesktop.org
> Cc: Lin, Shuicheng <shuicheng.lin at intel.com>; Roper, Matthew D
> <matthew.d.roper at intel.com>
> Subject: [PATCH] drm/xe: use xe_mmio_read32() to read mtcfg register
> 
> The mtcfg register is a 32-bit register and should therefore be accessed using
> xe_mmio_read32().
> 
> Other 3 changes per codestyle suggestion:
> "
> xe_mmio.c:83: CHECK: Alignment should match open parenthesis
> xe_mmio.c:131: CHECK: Comparison to NULL could be written "!xe-
> >mmio.regs"
> xe_mmio.c:315: CHECK: line length of 103 exceeds 100 columns "
> 

Probably it needs fixes tag?

> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Shuicheng Lin <shuicheng.lin at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_mmio.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 096c38cc51c8..7357458bc0d2 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -75,12 +75,12 @@ static void mmio_multi_tile_setup(struct xe_device
> *xe, size_t tile_mmio_size)
>  		 * is fine as it's going to the root tile's mmio, that's
>  		 * guaranteed to be initialized earlier in
> xe_mmio_probe_early()
>  		 */
> -		mtcfg = xe_mmio_read64_2x32(mmio, XEHP_MTCFG_ADDR);
> +		mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR);

Yes it is 32 bit reg. 

>  		tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
> 
>  		if (tile_count < xe->info.tile_count) {
>  			drm_info(&xe->drm, "tile_count: %d,
> reduced_tile_count %d\n",
> -					xe->info.tile_count, tile_count);
> +				 xe->info.tile_count, tile_count);
>  			xe->info.tile_count = tile_count;
> 
>  			/*
> @@ -128,7 +128,7 @@ int xe_mmio_probe_early(struct xe_device *xe)
>  	 */
>  	xe->mmio.size = pci_resource_len(pdev, GTTMMADR_BAR);
>  	xe->mmio.regs = pci_iomap(pdev, GTTMMADR_BAR, 0);
> -	if (xe->mmio.regs == NULL) {
> +	if (!xe->mmio.regs) {

Not sure if this is needed. Everyway apart from above minor comment this is,
Reviewed-by: Tejas Upadhyay <tejas.upadhyay at intel.com>

Tejas
>  		drm_err(&xe->drm, "failed to map registers\n");
>  		return -EIO;
>  	}
> @@ -312,8 +312,8 @@ u64 xe_mmio_read64_2x32(struct xe_mmio *mmio,
> struct xe_reg reg)
>  	return (u64)udw << 32 | ldw;
>  }
> 
> -static int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32
> mask, u32 val, u32 timeout_us,
> -			    u32 *out_val, bool atomic, bool expect_match)
> +static int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32
> mask, u32 val,
> +			    u32 timeout_us, u32 *out_val, bool atomic, bool
> expect_match)
>  {
>  	ktime_t cur = ktime_get_raw();
>  	const ktime_t end = ktime_add_us(cur, timeout_us);
> --
> 2.25.1