[PATCH v1 5/7] drm/xe/vf: Rebase HWSP of all contexts after migration
Tomasz Lis
tomasz.lis at intel.com
Tue May 13 22:49:50 UTC 2025
All contexts require an update due to GGTT range shift, as that
affects their HWSP.
The HW status page of a context contains GGTT references, which
need to be shifted to a new range (or re-computed using the
previously updated vma nodes). The references include ring start
address and indirect state address.
Signed-off-by: Tomasz Lis <tomasz.lis at intel.com>
---
drivers/gpu/drm/xe/xe_lrc.c | 18 ++++++++++++++++
drivers/gpu/drm/xe/xe_lrc.h | 1 +
drivers/gpu/drm/xe/xe_sriov_vf.c | 35 ++++++++++++++++++++++++++++++--
3 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 61a2e87990a9..43e1c18e1769 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1184,6 +1184,24 @@ void xe_lrc_destroy(struct kref *ref)
kfree(lrc);
}
+/**
+ * xe_lrc_update_hwctx_regs_with_address - Re-compute GGTT references within given LRC.
+ * @lrc: the &xe_lrc struct instance
+ */
+void xe_lrc_update_hwctx_regs_with_address(struct xe_lrc *lrc)
+{
+ struct xe_gt *gt = lrc->fence_ctx.gt;
+
+ if (xe_gt_has_indirect_ring_state(gt)) {
+ xe_lrc_write_ctx_reg(lrc, CTX_INDIRECT_RING_STATE,
+ __xe_lrc_indirect_ring_ggtt_addr(lrc));
+
+ xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_START,
+ __xe_lrc_ring_ggtt_addr(lrc));
+ } else
+ xe_lrc_write_ctx_reg(lrc, CTX_RING_START, __xe_lrc_ring_ggtt_addr(lrc));
+}
+
void xe_lrc_set_ring_tail(struct xe_lrc *lrc, u32 tail)
{
if (xe_lrc_has_indirect_ring_state(lrc))
diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
index eb6e8de8c939..e7a99cfd0abe 100644
--- a/drivers/gpu/drm/xe/xe_lrc.h
+++ b/drivers/gpu/drm/xe/xe_lrc.h
@@ -88,6 +88,7 @@ bool xe_lrc_ring_is_idle(struct xe_lrc *lrc);
u32 xe_lrc_indirect_ring_ggtt_addr(struct xe_lrc *lrc);
u32 xe_lrc_ggtt_addr(struct xe_lrc *lrc);
u32 *xe_lrc_regs(struct xe_lrc *lrc);
+void xe_lrc_update_hwctx_regs_with_address(struct xe_lrc *lrc);
u32 xe_lrc_read_ctx_reg(struct xe_lrc *lrc, int reg_nr);
void xe_lrc_write_ctx_reg(struct xe_lrc *lrc, int reg_nr, u32 val);
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf.c b/drivers/gpu/drm/xe/xe_sriov_vf.c
index ab91ac68ef5f..016faa29cddd 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf.c
@@ -7,12 +7,14 @@
#include "xe_assert.h"
#include "xe_device.h"
+#include "xe_exec_queue_types.h"
#include "xe_gt.h"
#include "xe_gt_sriov_printk.h"
#include "xe_gt_sriov_vf.h"
#include "xe_guc_ct.h"
#include "xe_guc_submit.h"
#include "xe_irq.h"
+#include "xe_lrc.h"
#include "xe_pm.h"
#include "xe_sriov.h"
#include "xe_sriov_printk.h"
@@ -223,6 +225,34 @@ static int vf_post_migration_requery_guc(struct xe_device *xe)
return ret;
}
+static void xe_exec_queue_contexts_hwsp_rebase(struct xe_exec_queue *eq)
+{
+ int i;
+
+ for (i = 0; i < eq->width; ++i)
+ xe_lrc_update_hwctx_regs_with_address(eq->lrc[i]);
+}
+
+static void xe_guc_contexts_hwsp_rebase(struct xe_guc *guc)
+{
+ struct xe_exec_queue *eq;
+ unsigned long index;
+
+ mutex_lock(&guc->submission_state.lock);
+ xa_for_each(&guc->submission_state.exec_queue_lookup, index, eq)
+ xe_exec_queue_contexts_hwsp_rebase(eq);
+ mutex_unlock(&guc->submission_state.lock);
+}
+
+static void vf_post_migration_fixup_contexts(struct xe_device *xe)
+{
+ struct xe_gt *gt;
+ unsigned int id;
+
+ for_each_gt(gt, xe, id)
+ xe_guc_contexts_hwsp_rebase(>->uc.guc);
+}
+
static void vf_post_migration_fixup_ctb(struct xe_device *xe)
{
struct xe_gt *gt;
@@ -303,9 +333,10 @@ static void vf_post_migration_recovery(struct xe_device *xe)
goto fail;
need_fixups = vf_post_migration_fixup_ggtt_nodes(xe);
- /* FIXME: add the recovery steps */
- if (need_fixups)
+ if (need_fixups) {
+ vf_post_migration_fixup_contexts(xe);
vf_post_migration_fixup_ctb(xe);
+ }
vf_post_migration_kickstart(xe);
vf_post_migration_notify_resfix_done(xe);
--
2.25.1
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