[PATCH 06/10] drm/xe/display: Dont poke into GGTT internals to fill a DPT

[Juha-Pekka Heikkilä]

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>

On Mon, May 5, 2025 at 3:20 PM Maarten Lankhorst <dev at lankhorst.se> wrote:
>
> For DPT, it is sufficient to get the GGTT encode flags to fill the DPT.
> Create a function to return the encode flags, and then encode using the
> BO address.
>
> Signed-off-by: Maarten Lankhorst <dev at lankhorst.se>
> ---
>  drivers/gpu/drm/xe/display/xe_fb_pin.c | 20 +++++++++-----------
>  drivers/gpu/drm/xe/xe_ggtt.c           | 15 +++++++++++++++
>  drivers/gpu/drm/xe/xe_ggtt.h           |  2 ++
>  3 files changed, 26 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index d509def82b134..5392e46a3a134 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -23,6 +23,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_
>         struct xe_device *xe = xe_bo_device(bo);
>         struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
>         u32 column, row;
> +       u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]);
>
>         /* TODO: Maybe rewrite so we can traverse the bo addresses sequentially,
>          * by writing dpt/ggtt in a different order?
> @@ -32,10 +33,9 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_
>                 u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
>
>                 for (row = 0; row < height; row++) {
> -                       u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
> -                                                             xe->pat.idx[XE_CACHE_NONE]);
> +                       u64 addr = xe_bo_addr(bo, src_idx * XE_PAGE_SIZE, XE_PAGE_SIZE);
>
> -                       iosys_map_wr(map, *dpt_ofs, u64, pte);
> +                       iosys_map_wr(map, *dpt_ofs, u64, pte | addr);
>                         *dpt_ofs += 8;
>                         src_idx -= src_stride;
>                 }
> @@ -55,17 +55,15 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs,
>  {
>         struct xe_device *xe = xe_bo_device(bo);
>         struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
> -       u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset, u16 pat_index)
> -               = ggtt->pt_ops->pte_encode_bo;
>         u32 column, row;
> +       u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]);
>
>         for (row = 0; row < height; row++) {
>                 u32 src_idx = src_stride * row + bo_ofs;
>
>                 for (column = 0; column < width; column++) {
> -                       iosys_map_wr(map, *dpt_ofs, u64,
> -                                    pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
> -                                    xe->pat.idx[XE_CACHE_NONE]));
> +                       u64 addr = xe_bo_addr(bo, src_idx * XE_PAGE_SIZE, XE_PAGE_SIZE);
> +                       iosys_map_wr(map, *dpt_ofs, u64, pte | addr);
>
>                         *dpt_ofs += 8;
>                         src_idx++;
> @@ -129,13 +127,13 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
>                 return PTR_ERR(dpt);
>
>         if (view->type == I915_GTT_VIEW_NORMAL) {
> +               u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]);
>                 u32 x;
>
>                 for (x = 0; x < size / XE_PAGE_SIZE; x++) {
> -                       u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x * XE_PAGE_SIZE,
> -                                                             xe->pat.idx[XE_CACHE_NONE]);
> +                       u64 addr = xe_bo_addr(bo, x * XE_PAGE_SIZE, XE_PAGE_SIZE);
>
> -                       iosys_map_wr(&dpt->vmap, x * 8, u64, pte);
> +                       iosys_map_wr(&dpt->vmap, x * 8, u64, pte | addr);
>                 }
>         } else if (view->type == I915_GTT_VIEW_REMAPPED) {
>                 const struct intel_remapped_info *remap_info = &view->remapped;
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 7526739034ea0..59097c7a494b2 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -911,3 +911,18 @@ u64 xe_ggtt_print_holes(struct xe_ggtt *ggtt, u64 alignment, struct drm_printer
>
>         return total;
>  }
> +
> +/**
> + * xe_ggtt_encode_pte_flags - Get PTE encoding flags for BO
> + * @ggtt: &xe_ggtt
> + * @bo: &xe_bo
> + * @pat_index: The pat_index for the PTE.
> + *
> + * This function returns the pte_flags for a given BO, without  address.
> + * It's used for DPT to fill a GGTT mapped BO with a linear lookup table.
> + */
> +u64 xe_ggtt_encode_pte_flags(struct xe_ggtt *ggtt,
> +                            struct xe_bo *bo, u16 pat_index)
> +{
> +       return ggtt->pt_ops->pte_encode_flags(bo, pat_index);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h
> index c48da99908848..437ba65f33860 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.h
> +++ b/drivers/gpu/drm/xe/xe_ggtt.h
> @@ -49,4 +49,6 @@ static inline void xe_ggtt_might_lock(struct xe_ggtt *ggtt)
>  void xe_ggtt_might_lock(struct xe_ggtt *ggtt);
>  #endif
>
> +u64 xe_ggtt_encode_pte_flags(struct xe_ggtt *ggtt, struct xe_bo *bo, u16 pat_index);
> +
>  #endif
> --
> 2.45.2
>