[PATCH v2 07/12] drm/i915/flipq: Provide the nuts and bolts code for flip queue

[Shankar, Uma]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Sent: Wednesday, May 21, 2025 11:11 PM
> To: Shankar, Uma <uma.shankar at intel.com>
> Cc: intel-gfx at lists.freedesktop.org; intel-xe at lists.freedesktop.org
> Subject: Re: [PATCH v2 07/12] drm/i915/flipq: Provide the nuts and bolts code for
> flip queue
> 
> On Tue, May 20, 2025 at 07:06:42AM +0000, Shankar, Uma wrote:
> > > +static int intel_flipq_exec_time_us(struct intel_display *display) {
> > > +	/* TODO ask the DSB code what this should be */
> > > +	int dsb_exec_time = 20;
> >
> > I think optimum value would be 100.
> > From bspec: "For the flip queue use case, the recommended DSB execution time
> is 100us + one SAGV block time"
> 
> That's just a random number someone pulled out of a hat. We currently use 20
> usec for the arming registers writes, and we don't have any estimate for the non-
> arming stuff since we don't need it. But for flip queue we need to guesstimate the
> whole thing, so I suppose I might as well slap in a 80usec for the non-arming part
> now.

Agree, this is more of an empirical value provided. Yeah would be good to have this
extra buffer.

> Ideally we should calculate this based on how many registers we are writing, but
> that would require measuring the DSB execution speed and coming up with a
> reasonable formula for it...

Agree, it depends on the number or registers. We can extend this later to get an optimum value,
especially where we have just 2-3 registers to update vs 1000 of regs for luts etc.

Regards,
Uma Shankar

> --
> Ville Syrjälä
> Intel