[PATCH v10 0/5] drm/xe/hwmon: Add mailbox power limits, PL2, read energy from PMT
Karthik Poosa
karthik.poosa at intel.com
Fri May 23 15:00:09 UTC 2025
Add support manage power limits through pcode mailboxes.
Enable PL2 support through powerX_cap.
Expose PL2 interval through powerX_cap_interval.
Read energy status from PMT instead of MMIO.
Move power2_crit to power1_crit.
v2:
- Addressed review comments from Badal.
- Clamp the power limits maximum to BIOS default value due to
HSD:16027383332.
v3:
- Clamp power limit write also to BIOS default for platforms
with mailbox support.
- Enable power label if any of PL1 or PL2 is enabled.
- Address review comments in v2.
v4:
- Remove unncessary debug prints.
- Rebase.
v5:
- Resolve unused variable compiler warning.
- Add a return value check.
v6:
- Address kernel-doc build error.
- Rebase.
v7:
- Rebase.
Patch series history:
https://patchwork.freedesktop.org/series/148148/ - RFC
https://patchwork.freedesktop.org/series/148506/
https://patchwork.freedesktop.org/series/148811/
https://patchwork.freedesktop.org/series/148819/
https://patchwork.freedesktop.org/series/148926/
https://patchwork.freedesktop.org/series/149026/
Karthik Poosa (5):
drm/xe/hwmon: Add support to manage power limits though mailbox
drm/xe/hwmon: Move card reactive critical power under channel card
drm/xe/hwmon: Add support to manage PL2 though mailbox
drm/xe/hwmon: Expose powerX_cap_interval
drm/xe/hwmon: Read energy status from PMT
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 68 ++-
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 10 +-
drivers/gpu/drm/xe/regs/xe_pcode_regs.h | 6 -
drivers/gpu/drm/xe/regs/xe_pmt.h | 5 +
drivers/gpu/drm/xe/xe_device_types.h | 4 +
drivers/gpu/drm/xe/xe_hwmon.c | 488 +++++++++++++-----
drivers/gpu/drm/xe/xe_pci.c | 5 +
drivers/gpu/drm/xe/xe_pcode.c | 11 +
drivers/gpu/drm/xe/xe_pcode.h | 3 +
drivers/gpu/drm/xe/xe_pcode_api.h | 7 +
drivers/gpu/drm/xe/xe_vsec.c | 4 +-
drivers/gpu/drm/xe/xe_vsec.h | 4 +
12 files changed, 477 insertions(+), 138 deletions(-)
--
2.25.1
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