✗ CI.checkpatch: warning for Panel Replay + Adaptive sync (rev6)
Patchwork
patchwork at emeril.freedesktop.org
Wed May 28 20:06:48 UTC 2025
== Series Details ==
Series: Panel Replay + Adaptive sync (rev6)
URL : https://patchwork.freedesktop.org/series/149487/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
202708c00696422fd217223bb679a353a5936e23
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 394fd9cdd0af97f5122752db711f0251aa2469c5
Author: Jouni Högander <jouni.hogander at intel.com>
Date: Mon May 26 15:05:12 2025 +0300
drm/i915/psr: Do not disable Panel Replay in case VRR is enabled
Allow Panel Replay with VRR. All VRR modes are supposed to work with
Panel Replay.
Bspec: 68920, 68925
Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
+ /mt/dim checkpatch 76d59d6988dc9194cbd7d3c551c11f47f56f4020 drm-intel
db23a015e389 drm/panelreplay: Panel Replay capability DPCD register definitions
eeac4dcbacf2 drm/dp: Add Panel Replay capability bits from DP2.1 specification
-:33: WARNING:LONG_LINE: line length of 136 exceeds 100 columns
#33: FILE: include/drm/display/drm_dp.h:559:
+# define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK (3 << DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT)
total: 0 errors, 1 warnings, 0 checks, 20 lines checked
59003bef27c2 drm/i915/psr: Read all Panel Replay capability registers from DPCD
c10a66cb1c58 drm/i915/alpm: Add PR_ALPM_CTL register definitions
-:29: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#29: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:275:
+#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)
-:30: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#30: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:276:
+#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)
-:31: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#31: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:277:
+#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)
total: 0 errors, 3 warnings, 0 checks, 16 lines checked
571ab7247ccd drm/i915/alpm: Write PR_ALPM_CTL register
-:32: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#32: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:357:
+ if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &
-:33: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#33: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:358:
+ DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))
total: 0 errors, 2 warnings, 0 checks, 20 lines checked
860fe591380d drm/i915/psr: Add interface to check if AUXLess ALPM is needed by PSR
479abdc71a7c drm/i915/alpm: Add new interface to check if AUXLess ALPM is used
9fef8bb82167 drm/i915/alpm: Move port alpm configuration
-:74: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#74: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:407:
+ PORT_ALPM_CTL_SILENCE_PERIOD(
-:77: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#77: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:410:
+ PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
-:79: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#79: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:412:
+ PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
-:81: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#81: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:414:
+ PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
total: 0 errors, 0 warnings, 4 checks, 93 lines checked
dbded5c0cc09 drm/i915/display: Add PHY_CMN1_CONTROL register definitions
b759e4f7ec79 drm/i915/display: Add function to configure LFPS sending
216a76fcb77c drm/i915/psr: Fix using wrong mask in REG_FIELD_PREP
-:25: WARNING:LONG_LINE: line length of 139 exceeds 100 columns
#25: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:338:
+#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)
-:28: WARNING:LONG_LINE: line length of 138 exceeds 100 columns
#28: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:340:
+#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)
total: 0 errors, 2 warnings, 0 checks, 10 lines checked
394fd9cdd0af drm/i915/psr: Do not disable Panel Replay in case VRR is enabled
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