[Libva] [PATCH 2/5] Remove the hard coded value to suppor the 4Kx4K encoding
yakui.zhao at intel.com
yakui.zhao at intel.com
Mon Oct 29 23:50:33 PDT 2012
From: Zhao Yakui <yakui.zhao at intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
---
src/gen6_mfc.c | 33 +++++++++++++++++++++++----------
src/gen75_mfc.c | 34 ++++++++++++++++++++++++----------
2 files changed, 47 insertions(+), 20 deletions(-)
diff --git a/src/gen6_mfc.c b/src/gen6_mfc.c
index 09d1110..760c3b1 100644
--- a/src/gen6_mfc.c
+++ b/src/gen6_mfc.c
@@ -536,13 +536,20 @@ gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *e
ADVANCE_BCS_BATCH(batch);
}
-static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+static void gen6_mfc_init(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
dri_bo *bo;
int i;
+ VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
+ int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
+ int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
+ width_in_mbs = ALIGN(width_in_mbs, 16);
+ height_in_mbs = ALIGN(width_in_mbs, 16);
/*Encode common setup for MFC*/
dri_bo_unreference(mfc_context->post_deblocking_output.bo);
mfc_context->post_deblocking_output.bo = NULL;
@@ -571,7 +578,7 @@ static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *en
dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 128 * 64,
+ width_in_mbs * 64,
64);
assert(bo);
mfc_context->intra_row_store_scratch_buffer.bo = bo;
@@ -579,7 +586,7 @@ static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *en
dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 128*128*16,
+ width_in_mbs * height_in_mbs * 16,
64);
assert(bo);
mfc_context->macroblock_status_buffer.bo = bo;
@@ -587,7 +594,7 @@ static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *en
dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 49152, /* 6 * 128 * 64 */
+ 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */
64);
assert(bo);
mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
@@ -595,7 +602,7 @@ static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *en
dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 12288, /* 1.5 * 128 * 64 */
+ 128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
0x1000);
assert(bo);
mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
@@ -673,6 +680,12 @@ static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
VAEncSliceParameterBufferH264 *slice_param;
VACodedBufferSegment *coded_buffer_segment;
unsigned char *flag = NULL;
+ VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
+ int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
+ int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
+
+ width_in_mbs = ALIGN(width_in_mbs, 16);
+ height_in_mbs = ALIGN(width_in_mbs, 16);
for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb == 0; j++) {
assert(encode_state->slice_params_ext && encode_state->slice_params_ext[j]->buffer);
@@ -706,12 +719,12 @@ static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
gen6_avc_surface->dmv_top =
dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 68*8192,
+ 68 * width_in_mbs * height_in_mbs,
64);
gen6_avc_surface->dmv_bottom =
dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 68*8192,
+ 68 * width_in_mbs * height_in_mbs,
64);
assert(gen6_avc_surface->dmv_top);
assert(gen6_avc_surface->dmv_bottom);
@@ -753,12 +766,12 @@ static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
gen6_avc_surface->dmv_top =
dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 68*8192,
+ 68 * width_in_mbs * height_in_mbs,
64);
gen6_avc_surface->dmv_bottom =
dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 68*8192,
+ 68 * width_in_mbs * height_in_mbs,
64);
assert(gen6_avc_surface->dmv_top);
assert(gen6_avc_surface->dmv_bottom);
@@ -1508,7 +1521,7 @@ gen6_mfc_avc_encode_picture(VADriverContextP ctx,
int sts;
for (;;) {
- gen6_mfc_init(ctx, encoder_context);
+ gen6_mfc_init(ctx, encode_state, encoder_context);
gen6_mfc_avc_prepare(ctx, encode_state, encoder_context);
/*Programing bcs pipeline*/
gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline
diff --git a/src/gen75_mfc.c b/src/gen75_mfc.c
index f15bd84..2a3d9e1 100644
--- a/src/gen75_mfc.c
+++ b/src/gen75_mfc.c
@@ -426,12 +426,20 @@ gen75_mfc_free_avc_surface(void **data)
*data = NULL;
}
-static void gen75_mfc_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
+static void gen75_mfc_init(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
dri_bo *bo;
int i;
+ VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
+ int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
+ int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
+
+ width_in_mbs = ALIGN(width_in_mbs, 16);
+ height_in_mbs = ALIGN(width_in_mbs, 16);
/*Encode common setup for MFC*/
dri_bo_unreference(mfc_context->post_deblocking_output.bo);
@@ -461,7 +469,7 @@ static void gen75_mfc_init(VADriverContextP ctx, struct intel_encoder_context *e
dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 128 * 64,
+ width_in_mbs * 64,
64);
assert(bo);
mfc_context->intra_row_store_scratch_buffer.bo = bo;
@@ -469,7 +477,7 @@ static void gen75_mfc_init(VADriverContextP ctx, struct intel_encoder_context *e
dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 128*128*16,
+ width_in_mbs * height_in_mbs * 16,
64);
assert(bo);
mfc_context->macroblock_status_buffer.bo = bo;
@@ -477,7 +485,7 @@ static void gen75_mfc_init(VADriverContextP ctx, struct intel_encoder_context *e
dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 49152, /* 6 * 128 * 64 */
+ 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */
64);
assert(bo);
mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
@@ -485,7 +493,7 @@ static void gen75_mfc_init(VADriverContextP ctx, struct intel_encoder_context *e
dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
bo = dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 12288, /* 1.5 * 128 * 64 */
+ 2 * width_in_mbs * 64, /* 2 * width_in_mbs * 64 */
0x1000);
assert(bo);
mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
@@ -865,6 +873,12 @@ static VAStatus gen75_mfc_avc_prepare(VADriverContextP ctx,
VAEncSliceParameterBufferH264 *slice_param;
VACodedBufferSegment *coded_buffer_segment;
unsigned char *flag = NULL;
+ VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
+ int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
+ int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
+
+ width_in_mbs = ALIGN(width_in_mbs, 16);
+ height_in_mbs = ALIGN(width_in_mbs, 16);
for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb == 0; j++) {
assert(encode_state->slice_params_ext && encode_state->slice_params_ext[j]->buffer);
@@ -898,12 +912,12 @@ static VAStatus gen75_mfc_avc_prepare(VADriverContextP ctx,
gen6_avc_surface->dmv_top =
dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 68*8192,
+ 68* width_in_mbs * height_in_mbs,
64);
gen6_avc_surface->dmv_bottom =
dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 68*8192,
+ 68* width_in_mbs * height_in_mbs,
64);
assert(gen6_avc_surface->dmv_top);
assert(gen6_avc_surface->dmv_bottom);
@@ -945,12 +959,12 @@ static VAStatus gen75_mfc_avc_prepare(VADriverContextP ctx,
gen6_avc_surface->dmv_top =
dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 68*8192,
+ 68* width_in_mbs * height_in_mbs,
64);
gen6_avc_surface->dmv_bottom =
dri_bo_alloc(i965->intel.bufmgr,
"Buffer",
- 68*8192,
+ 68* width_in_mbs * height_in_mbs,
64);
assert(gen6_avc_surface->dmv_top);
assert(gen6_avc_surface->dmv_bottom);
@@ -1854,7 +1868,7 @@ gen75_mfc_avc_encode_picture(VADriverContextP ctx,
int sts;
for (;;) {
- gen75_mfc_init(ctx, encoder_context);
+ gen75_mfc_init(ctx, encode_state, encoder_context);
gen75_mfc_avc_prepare(ctx, encode_state, encoder_context);
/*Programing bcs pipeline*/
gen75_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline
--
1.7.12-rc1
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