[Libva] [Libva-intel-driver PATCH 6/6] Add support of dump decoding register on BDW when GPU hang is triggered

[Zhao, Yakui]

From: Zhao Yakui <yakui.zhao at intel.com>

When the BDW GT3 is used, it will use the override_flag to dump the registers on 
Ring 0/1.
When the BDW GT1/GT2 is used, it will use the similar mechanism as that on
Ivy/Haswell. 

Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
---
 src/i965_drv_video.c |   64 ++++++++++++++++++++++++++++++++++++++++++++++++++
 src/intel_driver.c   |    9 ++++++-
 src/intel_driver.h   |    5 ++++
 3 files changed, 77 insertions(+), 1 deletion(-)

diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index ead82a8..34fc960 100755
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -2802,6 +2802,70 @@ void dump_decoding_register(VADriverContextP ctx, dri_bo *bo)
 		    dump_regs[i].name, *(ptr + i));
 	}
 	dri_bo_unmap(bo);
+    } else if (IS_GEN8(i965->intel.device_info)) {
+        dump_count = sizeof(dump_regs) / sizeof(mfd_reg);
+
+        if (i965->intel.dual_bsd) {
+	    intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING0);
+
+	    for (i = 0; i < dump_count; i++) {
+		BEGIN_BCS_BATCH(batch, 4);
+		OUT_BCS_BATCH(batch, MI_STORE_REG_IMM | (0 << 22) | 2);
+		OUT_BCS_BATCH(batch, GEN8_BSD0_BASE_OFFSET + dump_regs[i].reg_offset);
+		OUT_BCS_RELOC(batch, bo, I915_GEM_DOMAIN_INSTRUCTION, 0, i * 4);
+		OUT_BCS_BATCH(batch, 0);
+		ADVANCE_BCS_BATCH(batch);
+	    }
+	    intel_batchbuffer_end_atomic(batch);
+    	    dri_bo_map(bo, 0);
+    	    ptr = bo->virtual;
+	    for (i = 0; i < dump_count; i++) {
+	        fprintf(stderr, "the value of Reg %8x (%s) on BSD ring 0 is %x\n",
+		    dump_regs[i].reg_offset + GEN8_BSD0_BASE_OFFSET,
+		    dump_regs[i].name, *(ptr + i));
+	    }
+	    dri_bo_unmap(bo);
+
+	    intel_batchbuffer_start_atomic_bcs_override(batch, 0x1000, BSD_RING1);
+
+	    for (i = 0; i < dump_count; i++) {
+		BEGIN_BCS_BATCH(batch, 4);
+		OUT_BCS_BATCH(batch, MI_STORE_REG_IMM | (0 << 22) | 2);
+		OUT_BCS_BATCH(batch, GEN8_BSD1_BASE_OFFSET + dump_regs[i].reg_offset);
+		OUT_BCS_RELOC(batch, bo, I915_GEM_DOMAIN_INSTRUCTION, 0, i * 4);
+		OUT_BCS_BATCH(batch, 0);
+		ADVANCE_BCS_BATCH(batch);
+	    }
+	    intel_batchbuffer_end_atomic(batch);
+    	    dri_bo_map(bo, 0);
+    	    ptr = bo->virtual;
+	    for (i = 0; i < dump_count; i++) {
+	        fprintf(stderr, "the value of Reg %8x (%s) on BSD ring 1 is %x\n",
+		    dump_regs[i].reg_offset + GEN8_BSD1_BASE_OFFSET,
+		    dump_regs[i].name, *(ptr + i));
+	    }
+	    dri_bo_unmap(bo);
+        } else {
+	    intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
+
+	    for (i = 0; i < dump_count; i++) {
+		BEGIN_BCS_BATCH(batch, 4);
+		OUT_BCS_BATCH(batch, MI_STORE_REG_IMM | (0 << 22) | 2);
+		OUT_BCS_BATCH(batch, GEN8_BSD0_BASE_OFFSET + dump_regs[i].reg_offset);
+		OUT_BCS_RELOC(batch, bo, I915_GEM_DOMAIN_INSTRUCTION, 0, i * 4);
+		OUT_BCS_BATCH(batch, 0);
+		ADVANCE_BCS_BATCH(batch);
+	    }
+	    intel_batchbuffer_end_atomic(batch);
+    	    dri_bo_map(bo, 0);
+    	    ptr = bo->virtual;
+	    for (i = 0; i < dump_count; i++) {
+	        fprintf(stderr, "the value of Reg %8x (%s) is %x\n",
+		    dump_regs[i].reg_offset + GEN8_BSD0_BASE_OFFSET,
+		    dump_regs[i].name, *(ptr + i));
+	    }
+	    dri_bo_unmap(bo);
+        }
     }
 
 }
diff --git a/src/intel_driver.c b/src/intel_driver.c
index 9e93efb..3bd5034 100644
--- a/src/intel_driver.c
+++ b/src/intel_driver.c
@@ -36,6 +36,8 @@
 #include "intel_driver.h"
 uint32_t g_intel_debug_option_flags = 0;
 
+#define LOCAL_I915_PARAM_HAS_BSD2	29
+
 static Bool
 intel_driver_get_param(struct intel_driver_data *intel, int param, int *value)
 {
@@ -77,6 +79,7 @@ intel_driver_init(VADriverContextP ctx)
     struct drm_state * const drm_state = (struct drm_state *)ctx->drm_state;
     int has_exec2 = 0, has_bsd = 0, has_blt = 0, has_vebox = 0;
     char *env_str = NULL;
+    int ret_value = 0;
 
     g_intel_debug_option_flags = 0;
     if ((env_str = getenv("VA_INTEL_DEBUG"))) {
@@ -122,7 +125,11 @@ intel_driver_init(VADriverContextP ctx)
         intel->has_blt = has_blt;
     if (intel_driver_get_param(intel, I915_PARAM_HAS_VEBOX, &has_vebox))
         intel->has_vebox = !!has_vebox;
-   
+
+    intel->dual_bsd = 0;
+    if (intel_driver_get_param(intel, LOCAL_I915_PARAM_HAS_BSD2, &ret_value))
+        intel->dual_bsd = !!ret_value;
+
     intel_driver_get_revid(intel, &intel->revision);
     intel_memman_init(intel);
     return true;
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 9df9e8d..c461670 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -157,6 +157,7 @@ struct intel_driver_data
     unsigned int has_bsd    : 1; /* Flag: has bitstream decoder for H.264? */
     unsigned int has_blt    : 1; /* Flag: has BLT unit? */
     unsigned int has_vebox  : 1; /* Flag: has VEBOX unit */
+    unsigned int dual_bsd   : 1; /* flag: Dual bsd ring */
 
     const struct intel_device_info *device_info;
 };
@@ -211,6 +212,10 @@ struct intel_region
 #define MFD_MC_READ_COUNT		0x84
 #define MFD_MC_MISS_COUNT		0x88
 
+#define GEN8_BSD0_BASE_OFFSET		0x12800
+#define GEN8_BSD1_BASE_OFFSET		0x1C800
+
+
 typedef struct _mfd_reg_ {
 	uint32_t reg_offset;
 	char *name;
-- 
1.7.10.1