[Libva] [Libva-intel-driver PATCH 21/25] SKL: The SEND with EOT message must use register 112-127 as source register

[Xiang, Haihao]

Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
Acked-by: Zhao Yakui <yakui.zhao at intel.com>
---
 src/shaders/render/exa_wm_write.g9a | 26 +++++++++++++-------------
 src/shaders/render/exa_wm_write.g9b | 22 +++++++++++-----------
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/src/shaders/render/exa_wm_write.g9a b/src/shaders/render/exa_wm_write.g9a
index 9c5a03c..5275cdc 100644
--- a/src/shaders/render/exa_wm_write.g9a
+++ b/src/shaders/render/exa_wm_write.g9a
@@ -25,25 +25,25 @@
 include(`exa_wm.g4i')
 
 /* header */
-define(`data_port_msg_2_0',     `g64')
-define(`data_port_msg_2_1',     `g65')
-define(`data_port_msg_2_ind',   `64')
+define(`data_port_msg_2_0',     `g112')
+define(`data_port_msg_2_1',     `g113')
+define(`data_port_msg_2_ind',   `112')
 
 mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable};
 mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable};
 
 /*
- * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel,
- * g70-g71 for Blue and g72-g73 for Alpha channel
+ * Prepare data in g114-g115 for Red channel, g116-g117 for Green channel,
+ * g118-g119 for Blue and g120-g121 for Alpha channel
  */
-define(`slot_r_00',     `g66')
-define(`slot_r_01',     `g67')
-define(`slot_g_00',     `g68')
-define(`slot_g_01',     `g69')
-define(`slot_b_00',     `g70')
-define(`slot_b_01',     `g71')
-define(`slot_a_00',     `g72')
-define(`slot_a_01',     `g73')
+define(`slot_r_00',     `g114')
+define(`slot_r_01',     `g115')
+define(`slot_g_00',     `g116')
+define(`slot_g_01',     `g117')
+define(`slot_b_00',     `g118')
+define(`slot_b_01',     `g119')
+define(`slot_a_00',     `g120')
+define(`slot_a_01',     `g121')
 
 mov (8) slot_r_00<1>F     src_sample_r_01<8,8,1>F { align1 mask_disable };
 mov (8) slot_r_01<1>F     src_sample_r_23<8,8,1>F { align1 mask_disable };
diff --git a/src/shaders/render/exa_wm_write.g9b b/src/shaders/render/exa_wm_write.g9b
index 413cfd6..e625b9d 100644
--- a/src/shaders/render/exa_wm_write.g9b
+++ b/src/shaders/render/exa_wm_write.g9b
@@ -1,14 +1,14 @@
-   { 0x00600001, 0x2800020c, 0x008d0000, 0x00000000 },
-   { 0x00600001, 0x2820020c, 0x008d0020, 0x00000000 },
-   { 0x00600001, 0x28403aec, 0x008d01c0, 0x00000000 },
-   { 0x00600001, 0x28603aec, 0x008d01e0, 0x00000000 },
-   { 0x00600001, 0x28803aec, 0x008d0200, 0x00000000 },
-   { 0x00600001, 0x28a03aec, 0x008d0220, 0x00000000 },
-   { 0x00600001, 0x28c03aec, 0x008d0240, 0x00000000 },
-   { 0x00600001, 0x28e03aec, 0x008d0260, 0x00000000 },
-   { 0x00600001, 0x29003aec, 0x008d0280, 0x00000000 },
-   { 0x00600001, 0x29203aec, 0x008d02a0, 0x00000000 },
-   { 0x05800031, 0x20000a40, 0x06000800, 0x940b1000 },
+   { 0x00600001, 0x2e00020c, 0x008d0000, 0x00000000 },
+   { 0x00600001, 0x2e20020c, 0x008d0020, 0x00000000 },
+   { 0x00600001, 0x2e403aec, 0x008d01c0, 0x00000000 },
+   { 0x00600001, 0x2e603aec, 0x008d01e0, 0x00000000 },
+   { 0x00600001, 0x2e803aec, 0x008d0200, 0x00000000 },
+   { 0x00600001, 0x2ea03aec, 0x008d0220, 0x00000000 },
+   { 0x00600001, 0x2ec03aec, 0x008d0240, 0x00000000 },
+   { 0x00600001, 0x2ee03aec, 0x008d0260, 0x00000000 },
+   { 0x00600001, 0x2f003aec, 0x008d0280, 0x00000000 },
+   { 0x00600001, 0x2f203aec, 0x008d02a0, 0x00000000 },
+   { 0x05800031, 0x20000a40, 0x06000e00, 0x940b1000 },
    { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
    { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
    { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
-- 
1.9.1