[Libva] [Libva-intel-driver PATCH 22/25] Add the initial support for VPP on SKL
Xiang, Haihao
haihao.xiang at intel.com
Mon Nov 17 20:45:28 PST 2014
There are only a few changes on media pipeline between BDW
and SKL, so we can reuse most BDW VPP code. I will follow the DOCs
to fix media pipeline states for SKL and add shaders for each
processing
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
---
src/Makefile.am | 2 +
src/gen8_post_processing.c | 62 ++++------
src/gen8_post_processing.h | 58 +++++++++
src/gen9_post_processing.c | 303 +++++++++++++++++++++++++++++++++++++++++++++
src/i965_device_info.c | 5 +-
5 files changed, 390 insertions(+), 40 deletions(-)
create mode 100644 src/gen8_post_processing.h
create mode 100644 src/gen9_post_processing.c
diff --git a/src/Makefile.am b/src/Makefile.am
index 70a3357..2968dba 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -68,6 +68,7 @@ source_c = \
gen75_vme.c \
gen75_vpp_gpe.c \
gen75_vpp_vebox.c \
+ gen9_post_processing.c \
i965_avc_bsd.c \
i965_avc_hw_scoreboard.c\
i965_avc_ildb.c \
@@ -102,6 +103,7 @@ source_h = \
gen75_picture_process.h \
gen75_vpp_gpe.h \
gen75_vpp_vebox.h \
+ gen8_post_processing.h \
i965_avc_bsd.h \
i965_avc_hw_scoreboard.h\
i965_avc_ildb.h \
diff --git a/src/gen8_post_processing.c b/src/gen8_post_processing.c
index bdd9728..25b6ac6 100644
--- a/src/gen8_post_processing.c
+++ b/src/gen8_post_processing.c
@@ -41,6 +41,8 @@
#include "i965_render.h"
#include "intel_media.h"
+#include "gen8_post_processing.h"
+
#define HAS_BLENDING(ctx) ((ctx)->codec_info->has_blending)
#define SURFACE_STATE_PADDED_SIZE SURFACE_STATE_PADDED_SIZE_GEN8
@@ -54,28 +56,6 @@
#define VA_STATUS_SUCCESS_1 0xFFFFFFFE
-static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
- const struct i965_surface *src_surface,
- const VARectangle *src_rect,
- struct i965_surface *dst_surface,
- const VARectangle *dst_rect,
- void *filter_param);
-
-static VAStatus gen8_pp_nv12_blending_initialize(VADriverContextP ctx,
- struct i965_post_processing_context *pp_context,
- const struct i965_surface *src_surface,
- const VARectangle *src_rect,
- struct i965_surface *dst_surface,
- const VARectangle *dst_rect,
- void *filter_param);
-
-static VAStatus gen8_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
- const struct i965_surface *src_surface,
- const VARectangle *src_rect,
- struct i965_surface *dst_surface,
- const VARectangle *dst_rect,
- void *filter_param);
-
/* TODO: Modify the shader and then compile it again.
* Currently it is derived from Haswell*/
static const uint32_t pp_null_gen8[][4] = {
@@ -664,7 +644,7 @@ pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int
return 0;
}
-static VAStatus
+VAStatus
pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
const struct i965_surface *src_surface,
const VARectangle *src_rect,
@@ -765,7 +745,7 @@ static void gen7_update_src_surface_uv_offset(VADriverContextP ctx,
}
}
-static VAStatus
+VAStatus
gen8_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
const struct i965_surface *src_surface,
const VARectangle *src_rect,
@@ -1019,7 +999,7 @@ gen7_pp_blending_set_block_parameter(struct i965_post_processing_context *pp_con
return 0;
}
-static VAStatus
+VAStatus
gen8_pp_nv12_blending_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
const struct i965_surface *src_surface,
const VARectangle *src_rect,
@@ -1505,9 +1485,11 @@ gen8_post_processing_context_finalize(struct i965_post_processing_context *pp_co
#define VPP_CURBE_ALLOCATION_SIZE 32
void
-gen8_post_processing_context_init(VADriverContextP ctx,
- void *data,
- struct intel_batchbuffer *batch)
+gen8_post_processing_context_common_init(VADriverContextP ctx,
+ void *data,
+ struct pp_module *pp_modules,
+ int num_pp_modules,
+ struct intel_batchbuffer *batch)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
int i, kernel_size;
@@ -1516,20 +1498,18 @@ gen8_post_processing_context_init(VADriverContextP ctx,
struct pp_module *pp_module;
struct i965_post_processing_context *pp_context = data;
- {
- pp_context->vfe_gpu_state.max_num_threads = 60;
- pp_context->vfe_gpu_state.num_urb_entries = 59;
- pp_context->vfe_gpu_state.gpgpu_mode = 0;
- pp_context->vfe_gpu_state.urb_entry_size = 16 - 1;
- pp_context->vfe_gpu_state.curbe_allocation_size = VPP_CURBE_ALLOCATION_SIZE;
- }
+ pp_context->vfe_gpu_state.max_num_threads = 60;
+ pp_context->vfe_gpu_state.num_urb_entries = 59;
+ pp_context->vfe_gpu_state.gpgpu_mode = 0;
+ pp_context->vfe_gpu_state.urb_entry_size = 16 - 1;
+ pp_context->vfe_gpu_state.curbe_allocation_size = VPP_CURBE_ALLOCATION_SIZE;
pp_context->intel_post_processing = gen8_post_processing;
pp_context->finalize = gen8_post_processing_context_finalize;
- assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen8));
+ assert(ARRAY_ELEMS(pp_context->pp_modules) == num_pp_modules);
- memcpy(pp_context->pp_modules, pp_modules_gen8, sizeof(pp_context->pp_modules));
+ memcpy(pp_context->pp_modules, pp_modules, sizeof(pp_context->pp_modules));
kernel_size = 4096 ;
@@ -1590,4 +1570,10 @@ gen8_post_processing_context_init(VADriverContextP ctx,
pp_context->curbe_size = 256;
}
-
+void
+gen8_post_processing_context_init(VADriverContextP ctx,
+ void *data,
+ struct intel_batchbuffer *batch)
+{
+ gen8_post_processing_context_common_init(ctx, data, pp_modules_gen8, ARRAY_ELEMS(pp_modules_gen8), batch);
+}
diff --git a/src/gen8_post_processing.h b/src/gen8_post_processing.h
new file mode 100644
index 0000000..e54d33f
--- /dev/null
+++ b/src/gen8_post_processing.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _GEN8_POST_PROCESSING_H_
+#define _GEN8_POST_PROCESSING_H_
+
+VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
+ const struct i965_surface *src_surface,
+ const VARectangle *src_rect,
+ struct i965_surface *dst_surface,
+ const VARectangle *dst_rect,
+ void *filter_param);
+
+VAStatus
+gen8_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
+ const struct i965_surface *src_surface,
+ const VARectangle *src_rect,
+ struct i965_surface *dst_surface,
+ const VARectangle *dst_rect,
+ void *filter_param);
+
+VAStatus
+gen8_pp_nv12_blending_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
+ const struct i965_surface *src_surface,
+ const VARectangle *src_rect,
+ struct i965_surface *dst_surface,
+ const VARectangle *dst_rect,
+ void *filter_param);
+
+void
+gen8_post_processing_context_common_init(VADriverContextP ctx,
+ void *data,
+ struct pp_module *pp_modules,
+ int num_pp_modules,
+ struct intel_batchbuffer *batch);
+#endif
diff --git a/src/gen9_post_processing.c b/src/gen9_post_processing.c
new file mode 100644
index 0000000..8204955
--- /dev/null
+++ b/src/gen9_post_processing.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+
+#include "intel_batchbuffer.h"
+#include "intel_driver.h"
+#include "i965_defines.h"
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+#include "i965_post_processing.h"
+#include "i965_render.h"
+#include "intel_media.h"
+
+#include "gen8_post_processing.h"
+
+static const uint32_t pp_null_gen9[][4] = {
+};
+
+static const uint32_t pp_nv12_load_save_nv12_gen9[][4] = {
+};
+
+static const uint32_t pp_nv12_load_save_pl3_gen9[][4] = {
+};
+
+static const uint32_t pp_pl3_load_save_nv12_gen9[][4] = {
+};
+
+static const uint32_t pp_pl3_load_save_pl3_gen9[][4] = {
+};
+
+static const uint32_t pp_nv12_scaling_gen9[][4] = {
+};
+
+static const uint32_t pp_nv12_avs_gen9[][4] = {
+};
+
+static const uint32_t pp_nv12_dndi_gen9[][4] = {
+};
+
+static const uint32_t pp_nv12_dn_gen9[][4] = {
+};
+
+static const uint32_t pp_nv12_load_save_pa_gen9[][4] = {
+};
+
+static const uint32_t pp_pl3_load_save_pa_gen9[][4] = {
+};
+
+static const uint32_t pp_pa_load_save_nv12_gen9[][4] = {
+};
+
+static const uint32_t pp_pa_load_save_pl3_gen9[][4] = {
+};
+
+static const uint32_t pp_pa_load_save_pa_gen9[][4] = {
+};
+
+static const uint32_t pp_rgbx_load_save_nv12_gen9[][4] = {
+};
+
+static const uint32_t pp_nv12_load_save_rgbx_gen9[][4] = {
+};
+
+static const uint32_t pp_nv12_blending_gen9[][4] = {
+};
+
+static struct pp_module pp_modules_gen9[] = {
+ {
+ {
+ "NULL module (for testing)",
+ PP_NULL,
+ pp_null_gen9,
+ sizeof(pp_null_gen9),
+ NULL,
+ },
+
+ pp_null_initialize,
+ },
+
+ {
+ {
+ "NV12_NV12",
+ PP_NV12_LOAD_SAVE_N12,
+ pp_nv12_load_save_nv12_gen9,
+ sizeof(pp_nv12_load_save_nv12_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "NV12_PL3",
+ PP_NV12_LOAD_SAVE_PL3,
+ pp_nv12_load_save_pl3_gen9,
+ sizeof(pp_nv12_load_save_pl3_gen9),
+ NULL,
+ },
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "PL3_NV12",
+ PP_PL3_LOAD_SAVE_N12,
+ pp_pl3_load_save_nv12_gen9,
+ sizeof(pp_pl3_load_save_nv12_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "PL3_PL3",
+ PP_PL3_LOAD_SAVE_N12,
+ pp_pl3_load_save_pl3_gen9,
+ sizeof(pp_pl3_load_save_pl3_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "NV12 Scaling module",
+ PP_NV12_SCALING,
+ pp_nv12_scaling_gen9,
+ sizeof(pp_nv12_scaling_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "NV12 AVS module",
+ PP_NV12_AVS,
+ pp_nv12_avs_gen9,
+ sizeof(pp_nv12_avs_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "NV12 DNDI module",
+ PP_NV12_DNDI,
+ pp_nv12_dndi_gen9,
+ sizeof(pp_nv12_dndi_gen9),
+ NULL,
+ },
+
+ pp_null_initialize,
+ },
+
+ {
+ {
+ "NV12 DN module",
+ PP_NV12_DN,
+ pp_nv12_dn_gen9,
+ sizeof(pp_nv12_dn_gen9),
+ NULL,
+ },
+
+ pp_null_initialize,
+ },
+ {
+ {
+ "NV12_PA module",
+ PP_NV12_LOAD_SAVE_PA,
+ pp_nv12_load_save_pa_gen9,
+ sizeof(pp_nv12_load_save_pa_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "PL3_PA module",
+ PP_PL3_LOAD_SAVE_PA,
+ pp_pl3_load_save_pa_gen9,
+ sizeof(pp_pl3_load_save_pa_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "PA_NV12 module",
+ PP_PA_LOAD_SAVE_NV12,
+ pp_pa_load_save_nv12_gen9,
+ sizeof(pp_pa_load_save_nv12_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "PA_PL3 module",
+ PP_PA_LOAD_SAVE_PL3,
+ pp_pa_load_save_pl3_gen9,
+ sizeof(pp_pa_load_save_pl3_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "PA_PA module",
+ PP_PA_LOAD_SAVE_PA,
+ pp_pa_load_save_pa_gen9,
+ sizeof(pp_pa_load_save_pa_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "RGBX_NV12 module",
+ PP_RGBX_LOAD_SAVE_NV12,
+ pp_rgbx_load_save_nv12_gen9,
+ sizeof(pp_rgbx_load_save_nv12_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "NV12_RGBX module",
+ PP_NV12_LOAD_SAVE_RGBX,
+ pp_nv12_load_save_rgbx_gen9,
+ sizeof(pp_nv12_load_save_rgbx_gen9),
+ NULL,
+ },
+
+ gen8_pp_plx_avs_initialize,
+ },
+
+ {
+ {
+ "NV12_BLEND module",
+ PP_NV12_BLEND,
+ pp_nv12_blending_gen9,
+ sizeof(pp_nv12_blending_gen9),
+ NULL,
+ },
+
+ gen8_pp_nv12_blending_initialize,
+ },
+};
+
+void
+gen9_post_processing_context_init(VADriverContextP ctx,
+ void *data,
+ struct intel_batchbuffer *batch)
+{
+ gen8_post_processing_context_common_init(ctx, data, pp_modules_gen9, ARRAY_ELEMS(pp_modules_gen9), batch);
+}
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index 23fcf2c..4660765 100755
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -310,12 +310,13 @@ static struct hw_codec_info chv_hw_codec_info = {
};
extern struct hw_context *gen9_enc_hw_context_init(VADriverContextP, struct object_config *);
+extern void gen9_post_processing_context_init(VADriverContextP, void *, struct intel_batchbuffer *);
static struct hw_codec_info skl_hw_codec_info = {
.dec_hw_context_init = gen8_dec_hw_context_init,
.enc_hw_context_init = gen9_enc_hw_context_init,
.proc_hw_context_init = gen75_proc_context_init,
- .render_init = gen8_render_init,
- .post_processing_context_init = gen8_post_processing_context_init,
+ .render_init = gen9_render_init,
+ .post_processing_context_init = gen9_post_processing_context_init,
.max_width = 4096,
.max_height = 4096,
--
1.9.1
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