Mesa (master): i965: Add auxiliary surface field #defines for Broadwell.
Kenneth Graunke
kwg at kemper.freedesktop.org
Thu Jun 26 18:50:49 UTC 2014
Module: Mesa
Branch: master
Commit: a46cb6a971b136f41e24739551f6d36ecc1694c0
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a46cb6a971b136f41e24739551f6d36ecc1694c0
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Mar 6 09:18:14 2014 -0800
i965: Add auxiliary surface field #defines for Broadwell.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
---
src/mesa/drivers/dri/i965/brw_defines.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index f89b7a5..88d18a3 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -580,6 +580,16 @@
#define GEN7_SURFACE_MCS_ENABLE (1 << 0)
#define GEN7_SURFACE_MCS_PITCH_SHIFT 3
#define GEN7_SURFACE_MCS_PITCH_MASK INTEL_MASK(11, 3)
+#define GEN8_SURFACE_AUX_QPITCH_SHIFT 16
+#define GEN8_SURFACE_AUX_QPITCH_MASK INTEL_MASK(30, 16)
+#define GEN8_SURFACE_AUX_PITCH_SHIFT 3
+#define GEN8_SURFACE_AUX_PITCH_MASK INTEL_MASK(11, 3)
+#define GEN8_SURFACE_AUX_MODE_MASK INTEL_MASK(2, 0)
+
+#define GEN8_SURFACE_AUX_MODE_NONE 0
+#define GEN8_SURFACE_AUX_MODE_MCS 1
+#define GEN8_SURFACE_AUX_MODE_APPEND 2
+#define GEN8_SURFACE_AUX_MODE_HIZ 3
/* Surface state DW7 */
#define GEN7_SURFACE_CLEAR_COLOR_SHIFT 28
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