Mesa (master): i965: Make a function to check the conditions to use the blitter
Anuj Phogat
aphogat at kemper.freedesktop.org
Wed Feb 25 22:25:44 UTC 2015
Module: Mesa
Branch: master
Commit: 82f6d17300bcdf407bffddba03533c702fe262f3
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=82f6d17300bcdf407bffddba03533c702fe262f3
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Feb 12 18:49:13 2015 -0800
i965: Make a function to check the conditions to use the blitter
No functional changes in the patch. Just makes the code look cleaner.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 40 ++++++++++++++++++-------
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 2ad9c70..36c3b26 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2305,6 +2305,34 @@ can_blit_slice(struct intel_mipmap_tree *mt,
return true;
}
+static bool
+use_intel_mipree_map_blit(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ GLbitfield mode,
+ unsigned int level,
+ unsigned int slice)
+{
+ if (brw->has_llc &&
+ /* It's probably not worth swapping to the blit ring because of
+ * all the overhead involved.
+ */
+ !(mode & GL_MAP_WRITE_BIT) &&
+ !mt->compressed &&
+ (mt->tiling == I915_TILING_X ||
+ /* Prior to Sandybridge, the blitter can't handle Y tiling */
+ (brw->gen >= 6 && mt->tiling == I915_TILING_Y)) &&
+ can_blit_slice(mt, level, slice))
+ return true;
+
+ if (mt->tiling != I915_TILING_NONE &&
+ mt->bo->size >= brw->max_gtt_map_object_size) {
+ assert(can_blit_slice(mt, level, slice));
+ return true;
+ }
+
+ return false;
+}
+
/**
* Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
* exceed 32 bits but to diminish the likelihood subtle bugs in pointer
@@ -2352,17 +2380,7 @@ intel_miptree_map(struct brw_context *brw,
intel_miptree_map_etc(brw, mt, map, level, slice);
} else if (mt->stencil_mt && !(mode & BRW_MAP_DIRECT_BIT)) {
intel_miptree_map_depthstencil(brw, mt, map, level, slice);
- }
- else if (brw->has_llc &&
- !(mode & GL_MAP_WRITE_BIT) &&
- !mt->compressed &&
- (mt->tiling == I915_TILING_X ||
- (brw->gen >= 6 && mt->tiling == I915_TILING_Y)) &&
- can_blit_slice(mt, level, slice)) {
- intel_miptree_map_blit(brw, mt, map, level, slice);
- } else if (mt->tiling != I915_TILING_NONE &&
- mt->bo->size >= brw->max_gtt_map_object_size) {
- assert(can_blit_slice(mt, level, slice));
+ } else if (use_intel_mipree_map_blit(brw, mt, mode, level, slice)) {
intel_miptree_map_blit(brw, mt, map, level, slice);
#if defined(USE_SSE41)
} else if (!(mode & GL_MAP_WRITE_BIT) && !mt->compressed && cpu_has_sse4_1) {
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