Mesa (master): vc4: Write the alignment of level width consistently in validation.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: b3ea377f8629ada57c67632a89f0d2e9d2faf23c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3ea377f8629ada57c67632a89f0d2e9d2faf23c

Author: Eric Anholt <eric at anholt.net>
Date:   Mon Mar 23 16:34:24 2015 -0700

vc4: Write the alignment of level width consistently in validation.

16 / cpp happens to be the same as utile_w on the only raster format
supported (4 bytes per pixel), but simulator/hw source code generally
talks in terms of utiles.

---

 src/gallium/drivers/vc4/kernel/vc4_validate.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/vc4/kernel/vc4_validate.c b/src/gallium/drivers/vc4/kernel/vc4_validate.c
index 0691a8d..568b625 100644
--- a/src/gallium/drivers/vc4/kernel/vc4_validate.c
+++ b/src/gallium/drivers/vc4/kernel/vc4_validate.c
@@ -164,7 +164,7 @@ check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
 
 	switch (tiling_format) {
 	case VC4_TILING_FORMAT_LINEAR:
-		aligned_width = roundup(width, 16 / cpp);
+		aligned_width = roundup(width, utile_w);
 		aligned_height = height;
 		break;
 	case VC4_TILING_FORMAT_T:
@@ -951,7 +951,7 @@ reloc_tex(struct vc4_exec_info *exec,
 			aligned_height = roundup(level_height, utile_h);
 			break;
 		default:
-			aligned_width = roundup(level_width, 16 / cpp);
+			aligned_width = roundup(level_width, utile_w);
 			aligned_height = level_height;
 			break;
 		}