Mesa (master): i965/gen8: Remove gen<8 checks in gen8 code

[Chad Versace]

Module: Mesa
Branch: master
Commit: 82b324c24bc28ae99a6110706c85460b71d26077
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=82b324c24bc28ae99a6110706c85460b71d26077

Author: Chad Versace <chad.versace at intel.com>
Date:   Thu Oct  8 12:21:19 2015 -0700

i965/gen8: Remove gen<8 checks in gen8 code

Some assertions in gen8_surface_state.c checked for gen < 8.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>

---

 src/mesa/drivers/dri/i965/gen8_surface_state.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index e1e7704..18b8665 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -221,8 +221,8 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
        * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
        *  16 must be used."
        */
-      assert(brw->gen < 9 || mt->halign == 16);
-      assert(brw->gen < 8 || mt->num_samples > 1 || mt->halign == 16);
+      if (brw->gen >= 9 || mt->num_samples == 1)
+         assert(mt->halign == 16);
    }
 
    const uint32_t surf_type = translate_tex_target(target);
@@ -470,8 +470,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
        * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
        *  16 must be used."
        */
-      assert(brw->gen < 9 || mt->halign == 16);
-      assert(brw->gen < 8 || mt->num_samples > 1 || mt->halign == 16);
+      if (brw->gen >= 9 || mt->num_samples == 1)
+         assert(mt->halign == 16);
    }
 
    uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);