Mesa (master): nouveau: enable ARB_shader_clock on nv50 and nvc0

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: b1b189a0abf69530cf55749881baa1b3f7eca17f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1b189a0abf69530cf55749881baa1b3f7eca17f

Author: Boyan Ding <boyan.j.ding at gmail.com>
Date:   Tue Apr  4 22:44:47 2017 +0800

nouveau: enable ARB_shader_clock on nv50 and nvc0

v2: Also enable support on nv50

Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>

---

 docs/features.txt                              | 2 +-
 docs/relnotes/17.1.0.html                      | 2 +-
 src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 +-
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/docs/features.txt b/docs/features.txt
index 5cc109036b..edc56842b9 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -293,7 +293,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_ARB_seamless_cubemap_per_texture                   DONE (i965, nvc0, radeonsi, r600, softpipe, swr)
   GL_ARB_shader_atomic_counter_ops                      DONE (i965/gen7+, nvc0, radeonsi, softpipe)
   GL_ARB_shader_ballot                                  DONE (radeonsi)
-  GL_ARB_shader_clock                                   DONE (i965/gen7+, radeonsi)
+  GL_ARB_shader_clock                                   DONE (i965/gen7+, nv50, nvc0, radeonsi)
   GL_ARB_shader_draw_parameters                         DONE (i965, nvc0, radeonsi)
   GL_ARB_shader_group_vote                              DONE (nvc0, radeonsi)
   GL_ARB_shader_stencil_export                          DONE (i965/gen9+, radeonsi, softpipe, llvmpipe, swr)
diff --git a/docs/relnotes/17.1.0.html b/docs/relnotes/17.1.0.html
index 7419970283..0a5cabe4f1 100644
--- a/docs/relnotes/17.1.0.html
+++ b/docs/relnotes/17.1.0.html
@@ -46,7 +46,7 @@ Note: some of the new features are only available with certain drivers.
 <ul>
 <li>GL_ARB_gpu_shader_int64 on i965/gen8+, nvc0, radeonsi, softpipe, llvmpipe</li>
 <li>GL_ARB_shader_ballot on radeonsi</li>
-<li>GL_ARB_shader_clock on radeonsi</li>
+<li>GL_ARB_shader_clock on nv50, nvc0, radeonsi</li>
 <li>GL_ARB_shader_group_vote on radeonsi</li>
 <li>GL_ARB_sparse_buffer on radeonsi/CIK+</li>
 <li>GL_ARB_transform_feedback2 on i965/gen6</li>
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 9e8eeacdbd..76999495fd 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -199,6 +199,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
    case PIPE_CAP_TGSI_TEX_TXF_LZ:
+   case PIPE_CAP_TGSI_CLOCK:
       return 1;
    case PIPE_CAP_SEAMLESS_CUBE_MAP:
       return 1; /* class_3d >= NVA0_3D_CLASS; */
@@ -263,7 +264,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_DOUBLES:
    case PIPE_CAP_INT64:
    case PIPE_CAP_INT64_DIVMOD:
-   case PIPE_CAP_TGSI_CLOCK:
    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
    case PIPE_CAP_TGSI_BALLOT:
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 064848db4a..7ef9bf9c9c 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -247,6 +247,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_DOUBLES:
    case PIPE_CAP_INT64:
    case PIPE_CAP_TGSI_TEX_TXF_LZ:
+   case PIPE_CAP_TGSI_CLOCK:
       return 1;
    case PIPE_CAP_COMPUTE:
       return (class_3d < GP100_3D_CLASS);
@@ -287,7 +288,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_NATIVE_FENCE_FD:
    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
    case PIPE_CAP_INT64_DIVMOD:
-   case PIPE_CAP_TGSI_CLOCK:
    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
    case PIPE_CAP_TGSI_BALLOT:
       return 0;