Mesa (master): radeonsi: don' t flush sL1 conditionally in WAIT_ON_CE_COUNTER

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 404f524fe2a3e3cc0024b3b8f8dc2e592a8aafed
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=404f524fe2a3e3cc0024b3b8f8dc2e592a8aafed

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Jul 29 22:03:38 2017 +0200

radeonsi: don't flush sL1 conditionally in WAIT_ON_CE_COUNTER

I don't know the condition for the flush, but we better turn this off.
The sL1 flush is used when CE dumps stuff into a ring buffer and the ring
buffer wraps.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeonsi/si_state_draw.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index a5f5b7f98a..dfe423610b 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1145,10 +1145,10 @@ void si_ce_pre_draw_synchronization(struct si_context *sctx)
 {
 	if (sctx->ce_need_synchronization) {
 		radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
-		radeon_emit(sctx->ce_ib, 1);
+		radeon_emit(sctx->ce_ib, 1); /* 1 = increment CE counter */
 
 		radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
-		radeon_emit(sctx->b.gfx.cs, 1);
+		radeon_emit(sctx->b.gfx.cs, 0); /* 0 = don't flush sL1 conditionally */
 	}
 }
 
@@ -1156,7 +1156,7 @@ void si_ce_post_draw_synchronization(struct si_context *sctx)
 {
 	if (sctx->ce_need_synchronization) {
 		radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
-		radeon_emit(sctx->b.gfx.cs, 0);
+		radeon_emit(sctx->b.gfx.cs, 0); /* unused */
 
 		sctx->ce_need_synchronization = false;
 	}