Mesa (master): radeonsi: fix various CLEAR_STATE issues

[Marek Olšák]

Module: Mesa
Branch: master
Commit: b9fc9d3f241758ed8a274be7abf68bf448653508
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9fc9d3f241758ed8a274be7abf68bf448653508

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Jul 30 03:37:21 2017 +0200

radeonsi: fix various CLEAR_STATE issues

Fixes: 064550238ef0 ("radeonsi: use CLEAR_STATE to initialize some
                      registers")
Bugzilla: https://bugs.freedesktop.org/101969
Tested-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeonsi/si_state.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 7dadc4aa24..c151a980e0 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4549,10 +4549,32 @@ static void si_init_config(struct si_context *sctx)
 		}
 	}
 
+	/* CLEAR_STATE doesn't clear these correctly on certain generations.
+	 * I don't know why. Deduced by trial and error.
+	 */
+	if (sctx->b.chip_class <= CIK) {
+		si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
+		si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
+		si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
+		si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
+			       S_028244_BR_X(16384) | S_028244_BR_Y(16384));
+		si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
+		si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
+			       S_028034_BR_X(16384) | S_028034_BR_Y(16384));
+	}
+
 	if (sctx->b.chip_class >= GFX9) {
 		si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
 		si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
 		si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
+	} else {
+		/* These registers, when written, also overwrite the CLEAR_STATE
+		 * context, so we can't rely on CLEAR_STATE setting them.
+		 * It would be an issue if there was another UMD changing them.
+		 */
+		si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
+		si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
+		si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
 	}
 
 	if (sctx->b.chip_class >= CIK) {