Mesa (master): nvc0/ir: Properly lower 64-bit shifts when the shift value is >32

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 9bee12160bed72dae5cdb006ea38c40f89e174da
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bee12160bed72dae5cdb006ea38c40f89e174da

Author: Pierre Moreau <pierre.morrow at free.fr>
Date:   Sun Dec  3 21:28:57 2017 +0100

nvc0/ir: Properly lower 64-bit shifts when the shift value is >32

Fixes: 61d7676df77 "nvc0/ir: add support for 64-bit shift lowering on SM20/SM30"

Fixes fs-shift-scalar-by-scalar.shader_test from piglit for the current
set-up:

uniform int64_t ival -0x7dfcfefbdf6536ff # bit pattern: 0x82030104209ac901
uniform uint64_t uval 0x1400000085010203
uniform int shl 36
uniform int shr 36
uniform int64_t iexpected_shl 0x09ac901000000000
uniform int64_t iexpected_shr -0x7dfcff0 # bit pattern: 0xfffffffff8203010
uniform uint64_t uexpected_shl 0x5010203000000000
uniform uint64_t uexpected_shr 0x0000000001400000
draw rect ortho 12 0 4 4

Signed-off-by: Pierre Moreau <pierre.morrow at free.fr>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 7243b1d2e4..6b51b7607c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -216,7 +216,7 @@ NVC0LegalizeSSA::handleShift(Instruction *lo)
       // Compute LO (all shift values)
       bld.mkOp2(op, type, (dst[0] = bld.getSSA()), src[0], shift);
       // Compute HI (shift > 32)
-      bld.mkOp2(op, type, (hi2 = bld.getSSA()), src[1],
+      bld.mkOp2(op, type, (hi2 = bld.getSSA()), src[0],
                 bld.mkOp1v(OP_NEG, TYPE_S32, bld.getSSA(), x32_minus_shift))
          ->setPredicate(CC_NOT_P, pred);
       bld.mkOp2(OP_UNION, TYPE_U32, (dst[1] = bld.getSSA()), hi1, hi2);