Mesa (master): nv50/ir: return a register when retrieving thread id sysval

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 399e267f0e633df41eb1922f7c5f0958a40d6a52
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=399e267f0e633df41eb1922f7c5f0958a40d6a52

Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Sat Feb 11 20:23:30 2017 -0500

nv50/ir: return a register when retrieving thread id sysval

We have logic to short-circuit such retrievals to zero. However "zero"
was an immediate, and some logic expected to get registers (to later be
propagated). Fix this by using loadImm.

Fixes GL45-CTS.gpu_shader5.images_array_indexing

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 6ad8189..d634d2d 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2039,7 +2039,7 @@ Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
       assert(!ptr);
       if (info->sv[idx].sn == TGSI_SEMANTIC_THREAD_ID &&
           info->prop.cp.numThreads[swz] == 1)
-         return zero;
+         return loadImm(NULL, 0u);
       ld = mkOp1(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
       ld->perPatch = info->sv[idx].patch;
       return ld->getDef(0);