Mesa (master): gm107/ir: fix address offset bitfield for ATOMS

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 7e75f0913ab545be14feb233d1ed74dc48116fb8
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e75f0913ab545be14feb233d1ed74dc48116fb8

Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Sat Feb 11 18:20:50 2017 -0500

gm107/ir: fix address offset bitfield for ATOMS

Fixes GL45-CTS.compute_shader.atomic-case1 on Maxwell

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index f36838c..6de3f39 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -2538,7 +2538,7 @@ CodeEmitterGM107::emitATOMS()
 
    emitField(0x34, 4, subOp);
    emitGPR  (0x14, insn->src(1));
-   emitADDR (0x08, 0x12, 22, 0, insn->src(0));
+   emitADDR (0x08, 0x1e, 22, 2, insn->src(0));
    emitGPR  (0x00, insn->def(0));
 }