Mesa (master): intel/blorp: Only double the fast-clear rect alignment on HSW

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Module: Mesa
Branch: master
Commit: 1e6b32d08ccdf3b5666fcfc798fe2fbd1b6dc99c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e6b32d08ccdf3b5666fcfc798fe2fbd1b6dc99c

Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Fri Jun  7 15:13:30 2019 -0500

intel/blorp: Only double the fast-clear rect alignment on HSW

This restriction was accidentally added to the BSpec/PRM as an
unrestricted restriction starting with the HSW docs and it was never
removed.  However, it only ever applied to HSW and actually potentially
causes problems on BDW and above where we have mipmapped fast-clears.

Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

---

 src/intel/blorp/blorp_clear.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index d7668eac3ca..00447aa9690 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -259,16 +259,21 @@ get_fast_clear_rect(const struct isl_device *dev,
       x_scaledown = x_align / 2;
       y_scaledown = y_align / 2;
 
-      /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
-       * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
-       * Clear of Non-MultiSampled Render Target Restrictions":
-       *
-       *   Clear rectangle must be aligned to two times the number of
-       *   pixels in the table shown below due to 16x16 hashing across the
-       *   slice.
-       */
-      x_align *= 2;
-      y_align *= 2;
+      if (ISL_DEV_IS_HASWELL(dev)) {
+         /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
+          * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
+          * Clear of Non-MultiSampled Render Target Restrictions":
+          *
+          *   Clear rectangle must be aligned to two times the number of
+          *   pixels in the table shown below due to 16x16 hashing across the
+          *   slice.
+          *
+          * This restriction is only documented to exist on HSW GT3 but
+          * empirical evidence suggests that it's also needed GT2.
+          */
+         x_align *= 2;
+         y_align *= 2;
+      }
    } else {
       assert(aux_surf->usage == ISL_SURF_USAGE_MCS_BIT);