Mesa (master): intel/fs: Drop the fs_surface_builder
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gitlab-mirror at kemper.freedesktop.org
Fri Mar 1 01:57:38 UTC 2019
Module: Mesa
Branch: master
Commit: 9d437f948201abc56ef8be349012babe37ccfbe4
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d437f948201abc56ef8be349012babe37ccfbe4
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Feb 11 16:11:35 2019 -0600
intel/fs: Drop the fs_surface_builder
All of the actual abstraction (except possibly setting size_written)
happens as part of the logical opcodes. The only thing that the surface
builder is providing at this point is extra levels of functions to call
through. I'm going to be adding bindless image support soon and all the
extra abstraction here is just getting in the way.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
---
src/intel/Makefile.sources | 2 -
src/intel/compiler/brw_fs_nir.cpp | 361 ++++++++++++++------------
src/intel/compiler/brw_fs_surface_builder.cpp | 212 ---------------
src/intel/compiler/brw_fs_surface_builder.h | 89 -------
src/intel/compiler/meson.build | 2 -
5 files changed, 195 insertions(+), 471 deletions(-)
diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 94a28d370e8..a5c8828a6b6 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -69,8 +69,6 @@ COMPILER_FILES = \
compiler/brw_fs_register_coalesce.cpp \
compiler/brw_fs_saturate_propagation.cpp \
compiler/brw_fs_sel_peephole.cpp \
- compiler/brw_fs_surface_builder.cpp \
- compiler/brw_fs_surface_builder.h \
compiler/brw_fs_validate.cpp \
compiler/brw_fs_visitor.cpp \
compiler/brw_inst.h \
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 02f1e55eae3..95c45e4c9c3 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -23,13 +23,11 @@
#include "compiler/glsl/ir.h"
#include "brw_fs.h"
-#include "brw_fs_surface_builder.h"
#include "brw_nir.h"
#include "util/u_math.h"
#include "util/bitscan.h"
using namespace brw;
-using namespace brw::surface_access;
void
fs_visitor::emit_nir_code()
@@ -3369,18 +3367,16 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
cs_prog_data->uses_num_work_groups = true;
- fs_reg surf_index = brw_imm_ud(surface);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(surface);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1); /* num components */
/* Read the 3 GLuint components of gl_NumWorkGroups */
for (unsigned i = 0; i < 3; i++) {
- fs_reg read_result =
- emit_untyped_read(bld, surf_index,
- brw_imm_ud(i << 2),
- 1 /* dims */, 1 /* size */,
- BRW_PREDICATE_NONE);
- read_result.type = dest.type;
- bld.MOV(dest, read_result);
- dest = offset(dest, bld, 1);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = brw_imm_ud(i << 2);
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
+ offset(dest, bld, i), srcs, SURFACE_LOGICAL_NUM_SRCS);
}
break;
}
@@ -3430,8 +3426,10 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
assert(stage == MESA_SHADER_COMPUTE);
const unsigned bit_size = nir_dest_bit_size(instr->dest);
- fs_reg offset_reg = retype(get_nir_src(instr->src[0]),
- BRW_REGISTER_TYPE_UD);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[0]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
/* Make dest unsigned because that's what the temporary will be */
dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
@@ -3439,19 +3437,19 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
/* Read the vector */
if (nir_intrinsic_align(instr) >= 4) {
assert(nir_dest_bit_size(instr->dest) == 32);
- fs_reg read_result = emit_untyped_read(bld, brw_imm_ud(GEN7_BTI_SLM),
- offset_reg, 1 /* dims */,
- instr->num_components,
- BRW_PREDICATE_NONE);
- for (unsigned i = 0; i < instr->num_components; i++)
- bld.MOV(offset(dest, bld, i), offset(read_result, bld, i));
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ fs_inst *inst =
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
+ inst->size_written = instr->num_components * dispatch_width * 4;
} else {
assert(nir_dest_bit_size(instr->dest) <= 32);
assert(nir_dest_num_components(instr->dest) == 1);
- fs_reg read_result =
- emit_byte_scattered_read(bld, brw_imm_ud(GEN7_BTI_SLM), offset_reg,
- 1 /* dims */, 1, bit_size,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
+
+ fs_reg read_result = bld.vgrf(BRW_REGISTER_TYPE_UD);
+ bld.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
+ read_result, srcs, SURFACE_LOGICAL_NUM_SRCS);
bld.MOV(dest, read_result);
}
break;
@@ -3462,28 +3460,33 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
assert(stage == MESA_SHADER_COMPUTE);
const unsigned bit_size = nir_src_bit_size(instr->src[0]);
- fs_reg val_reg = get_nir_src(instr->src[0]);
- fs_reg offset_reg = retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_UD);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
- val_reg.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
+ fs_reg data = get_nir_src(instr->src[0]);
+ data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
assert(nir_intrinsic_write_mask(instr) ==
(1u << instr->num_components) - 1);
if (nir_intrinsic_align(instr) >= 4) {
assert(nir_src_bit_size(instr->src[0]) == 32);
assert(nir_src_num_components(instr->src[0]) <= 4);
- emit_untyped_write(bld, brw_imm_ud(GEN7_BTI_SLM), offset_reg, val_reg,
- 1 /* dims */, instr->num_components,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
} else {
assert(nir_src_bit_size(instr->src[0]) <= 32);
assert(nir_src_num_components(instr->src[0]) == 1);
- fs_reg write_src = bld.vgrf(BRW_REGISTER_TYPE_UD);
- bld.MOV(write_src, val_reg);
- emit_byte_scattered_write(bld, brw_imm_ud(GEN7_BTI_SLM), offset_reg,
- write_src, 1 /* dims */, bit_size,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
+
+ srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_UD);
+ bld.MOV(srcs[SURFACE_LOGICAL_SRC_DATA], data);
+
+ bld.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
}
break;
}
@@ -3595,7 +3598,7 @@ fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld,
brw_imm_ud(stage_prog_data->binding_table.ssbo_start));
}
- return surf_index;
+ return bld.emit_uniformize(surf_index);
}
static unsigned
@@ -3643,24 +3646,27 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
/* Get some metadata from the image intrinsic. */
const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
- const unsigned dims = image_intrinsic_coord_components(instr);
const GLenum format = nir_intrinsic_format(instr);
- const unsigned dest_components = nir_intrinsic_dest_components(instr);
- /* Get the arguments of the image intrinsic. */
- const fs_reg image = get_nir_image_intrinsic_image(bld, instr);
- const fs_reg coords = retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_UD);
- fs_reg tmp;
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] =
+ get_nir_image_intrinsic_image(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] =
+ brw_imm_ud(image_intrinsic_coord_components(instr));
/* Emit an image load, store or atomic op. */
if (instr->intrinsic == nir_intrinsic_image_load) {
- tmp = emit_typed_read(bld, image, coords, dims,
- instr->num_components);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ fs_inst *inst =
+ bld.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
+ inst->size_written = instr->num_components * dispatch_width * 4;
} else if (instr->intrinsic == nir_intrinsic_image_store) {
- const fs_reg src0 = get_nir_src(instr->src[3]);
- emit_typed_write(bld, image, coords, src0, dims,
- instr->num_components);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ srcs[SURFACE_LOGICAL_SRC_DATA] = get_nir_src(instr->src[3]);
+ bld.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
} else {
int op;
unsigned num_srcs = info->num_srcs;
@@ -3701,18 +3707,21 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
unreachable("Not reachable.");
}
- const fs_reg src0 = (num_srcs >= 4 ?
- get_nir_src(instr->src[3]) : fs_reg());
- const fs_reg src1 = (num_srcs >= 5 ?
- get_nir_src(instr->src[4]) : fs_reg());
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
- tmp = emit_typed_atomic(bld, image, coords, src0, src1, dims, 1, op);
- }
+ fs_reg data;
+ if (num_srcs >= 4)
+ data = get_nir_src(instr->src[3]);
+ if (num_srcs >= 5) {
+ fs_reg tmp = bld.vgrf(data.type, 2);
+ fs_reg sources[2] = { data, get_nir_src(instr->src[4]) };
+ bld.LOAD_PAYLOAD(tmp, sources, 2, 0);
+ data = tmp;
+ }
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
- /* Assign the result. */
- for (unsigned c = 0; c < dest_components; ++c) {
- bld.MOV(offset(retype(dest, tmp.type), bld, c),
- offset(tmp, bld, c));
+ bld.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
}
break;
}
@@ -3755,32 +3764,34 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
}
case nir_intrinsic_image_load_raw_intel: {
- const fs_reg image = get_nir_image_intrinsic_image(bld, instr);
- const fs_reg addr = retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_UD);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] =
+ get_nir_image_intrinsic_image(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
- fs_reg tmp = emit_untyped_read(bld, image, addr, 1,
- instr->num_components);
-
- for (unsigned c = 0; c < instr->num_components; ++c) {
- bld.MOV(offset(retype(dest, tmp.type), bld, c),
- offset(tmp, bld, c));
- }
+ fs_inst *inst =
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
+ inst->size_written = instr->num_components * dispatch_width * 4;
break;
}
case nir_intrinsic_image_store_raw_intel: {
- const fs_reg image = get_nir_image_intrinsic_image(bld, instr);
- const fs_reg addr = retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_UD);
- const fs_reg data = retype(get_nir_src(instr->src[2]),
- BRW_REGISTER_TYPE_UD);
-
if (stage == MESA_SHADER_FRAGMENT)
brw_wm_prog_data(prog_data)->has_side_effects = true;
- emit_untyped_write(bld, image, addr, data, 1,
- instr->num_components);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] =
+ get_nir_image_intrinsic_image(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_DATA] = get_nir_src(instr->src[2]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
break;
}
@@ -4067,9 +4078,11 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
assert(devinfo->gen >= 7);
const unsigned bit_size = nir_dest_bit_size(instr->dest);
- fs_reg surf_index = get_nir_ssbo_intrinsic_index(bld, instr);
- fs_reg offset_reg = retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_UD);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] =
+ get_nir_ssbo_intrinsic_index(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
/* Make dest unsigned because that's what the temporary will be */
dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
@@ -4077,19 +4090,19 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
/* Read the vector */
if (nir_intrinsic_align(instr) >= 4) {
assert(nir_dest_bit_size(instr->dest) == 32);
- fs_reg read_result = emit_untyped_read(bld, surf_index, offset_reg,
- 1 /* dims */,
- instr->num_components,
- BRW_PREDICATE_NONE);
- for (unsigned i = 0; i < instr->num_components; i++)
- bld.MOV(offset(dest, bld, i), offset(read_result, bld, i));
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ fs_inst *inst =
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
+ inst->size_written = instr->num_components * dispatch_width * 4;
} else {
assert(nir_dest_bit_size(instr->dest) <= 32);
assert(nir_dest_num_components(instr->dest) == 1);
- fs_reg read_result =
- emit_byte_scattered_read(bld, surf_index, offset_reg,
- 1 /* dims */, 1, bit_size,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
+
+ fs_reg read_result = bld.vgrf(BRW_REGISTER_TYPE_UD);
+ bld.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
+ read_result, srcs, SURFACE_LOGICAL_NUM_SRCS);
bld.MOV(dest, read_result);
}
break;
@@ -4102,29 +4115,34 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
brw_wm_prog_data(prog_data)->has_side_effects = true;
const unsigned bit_size = nir_src_bit_size(instr->src[0]);
- fs_reg val_reg = get_nir_src(instr->src[0]);
- fs_reg surf_index = get_nir_ssbo_intrinsic_index(bld, instr);
- fs_reg offset_reg = retype(get_nir_src(instr->src[2]),
- BRW_REGISTER_TYPE_UD);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] =
+ get_nir_ssbo_intrinsic_index(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[2]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
- val_reg.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
+ fs_reg data = get_nir_src(instr->src[0]);
+ data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
assert(nir_intrinsic_write_mask(instr) ==
(1u << instr->num_components) - 1);
if (nir_intrinsic_align(instr) >= 4) {
assert(nir_src_bit_size(instr->src[0]) == 32);
assert(nir_src_num_components(instr->src[0]) <= 4);
- emit_untyped_write(bld, surf_index, offset_reg, val_reg,
- 1 /* dims */, instr->num_components,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
} else {
assert(nir_src_bit_size(instr->src[0]) <= 32);
assert(nir_src_num_components(instr->src[0]) == 1);
- fs_reg write_src = bld.vgrf(BRW_REGISTER_TYPE_UD);
- bld.MOV(write_src, val_reg);
- emit_byte_scattered_write(bld, surf_index, offset_reg,
- write_src, 1 /* dims */, bit_size,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
+
+ srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_UD);
+ bld.MOV(srcs[SURFACE_LOGICAL_SRC_DATA], data);
+
+ bld.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
}
break;
}
@@ -4611,24 +4629,28 @@ fs_visitor::nir_emit_ssbo_atomic(const fs_builder &bld,
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
dest = get_nir_dest(instr->dest);
- fs_reg surface = get_nir_ssbo_intrinsic_index(bld, instr);
- fs_reg offset = get_nir_src(instr->src[1]);
- fs_reg data1;
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = get_nir_ssbo_intrinsic_index(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
+
+ fs_reg data;
if (op != BRW_AOP_INC && op != BRW_AOP_DEC && op != BRW_AOP_PREDEC)
- data1 = get_nir_src(instr->src[2]);
- fs_reg data2;
- if (op == BRW_AOP_CMPWR)
- data2 = get_nir_src(instr->src[3]);
+ data = get_nir_src(instr->src[2]);
+
+ if (op == BRW_AOP_CMPWR) {
+ fs_reg tmp = bld.vgrf(data.type, 2);
+ fs_reg sources[2] = { data, get_nir_src(instr->src[3]) };
+ bld.LOAD_PAYLOAD(tmp, sources, 2, 0);
+ data = tmp;
+ }
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
/* Emit the actual atomic operation */
- fs_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
- data1, data2,
- 1 /* dims */, 1 /* rsize */,
- op,
- BRW_PREDICATE_NONE);
- dest.type = atomic_result.type;
- bld.MOV(dest, atomic_result);
+ bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
}
void
@@ -4642,22 +4664,25 @@ fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder &bld,
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
dest = get_nir_dest(instr->dest);
- fs_reg surface = get_nir_ssbo_intrinsic_index(bld, instr);
- fs_reg offset = get_nir_src(instr->src[1]);
- fs_reg data1 = get_nir_src(instr->src[2]);
- fs_reg data2;
- if (op == BRW_AOP_FCMPWR)
- data2 = get_nir_src(instr->src[3]);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = get_nir_ssbo_intrinsic_index(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
+
+ fs_reg data = get_nir_src(instr->src[2]);
+ if (op == BRW_AOP_FCMPWR) {
+ fs_reg tmp = bld.vgrf(data.type, 2);
+ fs_reg sources[2] = { data, get_nir_src(instr->src[3]) };
+ bld.LOAD_PAYLOAD(tmp, sources, 2, 0);
+ data = tmp;
+ }
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
/* Emit the actual atomic operation */
- fs_reg atomic_result = emit_untyped_atomic_float(bld, surface, offset,
- data1, data2,
- 1 /* dims */, 1 /* rsize */,
- op,
- BRW_PREDICATE_NONE);
- dest.type = atomic_result.type;
- bld.MOV(dest, atomic_result);
+ bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
}
void
@@ -4668,35 +4693,37 @@ fs_visitor::nir_emit_shared_atomic(const fs_builder &bld,
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
dest = get_nir_dest(instr->dest);
- fs_reg surface = brw_imm_ud(GEN7_BTI_SLM);
- fs_reg offset;
- fs_reg data1;
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
+
+ fs_reg data;
if (op != BRW_AOP_INC && op != BRW_AOP_DEC && op != BRW_AOP_PREDEC)
- data1 = get_nir_src(instr->src[1]);
- fs_reg data2;
- if (op == BRW_AOP_CMPWR)
- data2 = get_nir_src(instr->src[2]);
+ data = get_nir_src(instr->src[1]);
+ if (op == BRW_AOP_CMPWR) {
+ fs_reg tmp = bld.vgrf(data.type, 2);
+ fs_reg sources[2] = { data, get_nir_src(instr->src[2]) };
+ bld.LOAD_PAYLOAD(tmp, sources, 2, 0);
+ data = tmp;
+ }
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
/* Get the offset */
if (nir_src_is_const(instr->src[0])) {
- offset = brw_imm_ud(instr->const_index[0] +
- nir_src_as_uint(instr->src[0]));
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
+ brw_imm_ud(instr->const_index[0] + nir_src_as_uint(instr->src[0]));
} else {
- offset = vgrf(glsl_type::uint_type);
- bld.ADD(offset,
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = vgrf(glsl_type::uint_type);
+ bld.ADD(srcs[SURFACE_LOGICAL_SRC_ADDRESS],
retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_UD),
brw_imm_ud(instr->const_index[0]));
}
/* Emit the actual atomic operation operation */
- fs_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
- data1, data2,
- 1 /* dims */, 1 /* rsize */,
- op,
- BRW_PREDICATE_NONE);
- dest.type = atomic_result.type;
- bld.MOV(dest, atomic_result);
+ bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
}
void
@@ -4707,33 +4734,35 @@ fs_visitor::nir_emit_shared_atomic_float(const fs_builder &bld,
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
dest = get_nir_dest(instr->dest);
- fs_reg surface = brw_imm_ud(GEN7_BTI_SLM);
- fs_reg offset;
- fs_reg data1 = get_nir_src(instr->src[1]);
- fs_reg data2;
- if (op == BRW_AOP_FCMPWR)
- data2 = get_nir_src(instr->src[2]);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
+
+ fs_reg data = get_nir_src(instr->src[1]);
+ if (op == BRW_AOP_FCMPWR) {
+ fs_reg tmp = bld.vgrf(data.type, 2);
+ fs_reg sources[2] = { data, get_nir_src(instr->src[2]) };
+ bld.LOAD_PAYLOAD(tmp, sources, 2, 0);
+ data = tmp;
+ }
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
/* Get the offset */
if (nir_src_is_const(instr->src[0])) {
- offset = brw_imm_ud(instr->const_index[0] +
- nir_src_as_uint(instr->src[0]));
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
+ brw_imm_ud(instr->const_index[0] + nir_src_as_uint(instr->src[0]));
} else {
- offset = vgrf(glsl_type::uint_type);
- bld.ADD(offset,
- retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_UD),
- brw_imm_ud(instr->const_index[0]));
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = vgrf(glsl_type::uint_type);
+ bld.ADD(srcs[SURFACE_LOGICAL_SRC_ADDRESS],
+ retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_UD),
+ brw_imm_ud(instr->const_index[0]));
}
/* Emit the actual atomic operation operation */
- fs_reg atomic_result = emit_untyped_atomic_float(bld, surface, offset,
- data1, data2,
- 1 /* dims */, 1 /* rsize */,
- op,
- BRW_PREDICATE_NONE);
- dest.type = atomic_result.type;
- bld.MOV(dest, atomic_result);
+ bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
}
void
diff --git a/src/intel/compiler/brw_fs_surface_builder.cpp b/src/intel/compiler/brw_fs_surface_builder.cpp
deleted file mode 100644
index 8121d468efe..00000000000
--- a/src/intel/compiler/brw_fs_surface_builder.cpp
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * Copyright © 2013-2015 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "isl/isl.h"
-#include "brw_fs_surface_builder.h"
-#include "brw_fs.h"
-
-using namespace brw;
-
-namespace brw {
- namespace surface_access {
- namespace {
- /**
- * Generate a logical send opcode for a surface message and return
- * the result.
- */
- fs_reg
- emit_send(const fs_builder &bld, enum opcode opcode,
- const fs_reg &addr, const fs_reg &src, const fs_reg &surface,
- unsigned dims, unsigned arg, unsigned rsize,
- brw_predicate pred = BRW_PREDICATE_NONE)
- {
- /* Reduce the dynamically uniform surface index to a single
- * scalar.
- */
- const fs_reg usurface = bld.emit_uniformize(surface);
- fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
- srcs[SURFACE_LOGICAL_SRC_ADDRESS] = addr;
- srcs[SURFACE_LOGICAL_SRC_DATA] = src;
- srcs[SURFACE_LOGICAL_SRC_SURFACE] = usurface;
- srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(dims);
- srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(arg);
-
- const fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, rsize);
- fs_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs));
-
- inst->size_written = rsize * dst.component_size(inst->exec_size);
- inst->predicate = pred;
- return dst;
- }
- }
-
- /**
- * Emit an untyped surface read opcode. \p dims determines the number
- * of components of the address and \p size the number of components of
- * the returned value.
- */
- fs_reg
- emit_untyped_read(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- unsigned dims, unsigned size,
- brw_predicate pred)
- {
- return emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
- addr, fs_reg(), surface, dims, size, size, pred);
- }
-
- /**
- * Emit an untyped surface write opcode. \p dims determines the number
- * of components of the address and \p size the number of components of
- * the argument.
- */
- void
- emit_untyped_write(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, const fs_reg &src,
- unsigned dims, unsigned size,
- brw_predicate pred)
- {
- emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
- addr, src, surface, dims, size, 0, pred);
- }
-
- /**
- * Emit an untyped surface atomic opcode. \p dims determines the number
- * of components of the address and \p rsize the number of components of
- * the returned value (either zero or one).
- */
- fs_reg
- emit_untyped_atomic(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- const fs_reg &src0, const fs_reg &src1,
- unsigned dims, unsigned rsize, unsigned op,
- brw_predicate pred)
- {
- /* FINISHME: Factor out this frequently recurring pattern into a
- * helper function.
- */
- const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
- const fs_reg srcs[] = { src0, src1 };
- const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, n);
- bld.LOAD_PAYLOAD(tmp, srcs, n, 0);
-
- return emit_send(bld, SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
- addr, tmp, surface, dims, op, rsize, pred);
- }
-
- /**
- * Emit an untyped surface atomic float opcode. \p dims determines the
- * number of components of the address and \p rsize the number of
- * components of the returned value (either zero or one).
- */
- fs_reg
- emit_untyped_atomic_float(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- const fs_reg &src0, const fs_reg &src1,
- unsigned dims, unsigned rsize, unsigned op,
- brw_predicate pred)
- {
- /* FINISHME: Factor out this frequently recurring pattern into a
- * helper function.
- */
- const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
- const fs_reg srcs[] = { src0, src1 };
- const fs_reg tmp = bld.vgrf(src0.type, n);
- bld.LOAD_PAYLOAD(tmp, srcs, n, 0);
-
- return emit_send(bld, SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
- addr, tmp, surface, dims, op, rsize, pred);
- }
-
- /**
- * Emit a typed surface read opcode. \p dims determines the number of
- * components of the address and \p size the number of components of the
- * returned value.
- */
- fs_reg
- emit_typed_read(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, unsigned dims, unsigned size)
- {
- return emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
- addr, fs_reg(), surface, dims, size, size);
- }
-
- /**
- * Emit a typed surface write opcode. \p dims determines the number of
- * components of the address and \p size the number of components of the
- * argument.
- */
- void
- emit_typed_write(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, const fs_reg &src,
- unsigned dims, unsigned size)
- {
- emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
- addr, src, surface, dims, size, 0);
- }
-
- /**
- * Emit a typed surface atomic opcode. \p dims determines the number of
- * components of the address and \p rsize the number of components of
- * the returned value (either zero or one).
- */
- fs_reg
- emit_typed_atomic(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr,
- const fs_reg &src0, const fs_reg &src1,
- unsigned dims, unsigned rsize, unsigned op,
- brw_predicate pred)
- {
- /* FINISHME: Factor out this frequently recurring pattern into a
- * helper function.
- */
- const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
- const fs_reg srcs[] = { src0, src1 };
- const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, n);
- bld.LOAD_PAYLOAD(tmp, srcs, n, 0);
-
- return emit_send(bld, SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
- addr, tmp, surface, dims, op, rsize);
- }
-
- fs_reg
- emit_byte_scattered_read(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- unsigned dims, unsigned size,
- unsigned bit_size, brw_predicate pred)
- {
- return emit_send(bld, SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
- addr, fs_reg(), surface, dims, bit_size, size, pred);
- }
-
- void
- emit_byte_scattered_write(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, const fs_reg &src,
- unsigned dims,
- unsigned bit_size, brw_predicate pred)
- {
- emit_send(bld, SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
- addr, src, surface, dims, bit_size, 0, pred);
- }
- }
-}
diff --git a/src/intel/compiler/brw_fs_surface_builder.h b/src/intel/compiler/brw_fs_surface_builder.h
deleted file mode 100644
index 8df5d25f4fa..00000000000
--- a/src/intel/compiler/brw_fs_surface_builder.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* -*- c++ -*- */
-/*
- * Copyright © 2013-2015 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#ifndef BRW_FS_SURFACE_BUILDER_H
-#define BRW_FS_SURFACE_BUILDER_H
-
-#include "brw_fs_builder.h"
-
-namespace brw {
- namespace surface_access {
- fs_reg
- emit_untyped_read(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- unsigned dims, unsigned size,
- brw_predicate pred = BRW_PREDICATE_NONE);
-
- void
- emit_untyped_write(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, const fs_reg &src,
- unsigned dims, unsigned size,
- brw_predicate pred = BRW_PREDICATE_NONE);
-
- fs_reg
- emit_untyped_atomic(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- const fs_reg &src0, const fs_reg &src1,
- unsigned dims, unsigned rsize, unsigned op,
- brw_predicate pred = BRW_PREDICATE_NONE);
-
- fs_reg
- emit_untyped_atomic_float(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- const fs_reg &src0, const fs_reg &src1,
- unsigned dims, unsigned rsize, unsigned op,
- brw_predicate pred);
-
- fs_reg
- emit_typed_read(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, unsigned dims, unsigned size);
-
- void
- emit_typed_write(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, const fs_reg &src,
- unsigned dims, unsigned size);
-
- fs_reg
- emit_typed_atomic(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr,
- const fs_reg &src0, const fs_reg &src1,
- unsigned dims, unsigned rsize, unsigned op,
- brw_predicate pred = BRW_PREDICATE_NONE);
-
- fs_reg
- emit_byte_scattered_read(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- unsigned dims, unsigned size,
- unsigned bit_size,
- brw_predicate pred = BRW_PREDICATE_NONE);
-
- void
- emit_byte_scattered_write(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, const fs_reg &src,
- unsigned dims,
- unsigned bit_size,
- brw_predicate pred = BRW_PREDICATE_NONE);
- }
-}
-#endif
diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build
index f8e5e2518fe..21614c5baf9 100644
--- a/src/intel/compiler/meson.build
+++ b/src/intel/compiler/meson.build
@@ -62,8 +62,6 @@ libintel_compiler_files = files(
'brw_fs_register_coalesce.cpp',
'brw_fs_saturate_propagation.cpp',
'brw_fs_sel_peephole.cpp',
- 'brw_fs_surface_builder.cpp',
- 'brw_fs_surface_builder.h',
'brw_fs_validate.cpp',
'brw_fs_visitor.cpp',
'brw_inst.h',
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