Mesa (19.3): 33 new commits
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Wed Nov 6 17:11:54 UTC 2019
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=15342abc5bac5e11e28be05148ae5dca18020e79
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Wed Nov 6 09:08:45 2019 -0800
Bump VERSION to 19.3.0-rc2
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=08501e77af55dc2ac6bc438b45a6506d2bf3a355
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Thu Oct 10 15:10:56 2019 -0700
meson: Add dep_glvnd to egl deps when building with glvnd
Otherwise if glvnd is not installed systemwide, but only in a prefix,
it's headers wont be found. This happens because if it's headers are in
/usr/include/ then another dependence will provide the necessary -I
arguments and compilation will work.
Fixes: 035ec7a2bb2d5e413ac945b8f012185a0e187d5e
("meson: Add support for EGL glvnd")
Acked-by: Eric Engestrom <eric at engestrom.ch>
(cherry picked from commit 5d085ad052aac1f35cef7b60c0e6ecad65a6807b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=49af89a0b988e7474c3628201b277222679d1eed
Author: Paulo Zanoni <paulo.r.zanoni at intel.com>
Date: Fri Nov 1 14:28:48 2019 -0700
intel/compiler: remove the operand restriction for src1 on GLK
Commit 5847de6e9afe implemented a restriction that applies to ICL, but
wrongly marked it as also applying to GLK. Reviewers or MR !1125
pointed this, and the commit history shows removal of GLK to parts of
the patch, but it turns there was still a left-over GLK check in the
code.
This code was breaking some of the i8vec2 tests on GLK, for example:
dEQP-VK.subgroups.arithmetic.compute.subgroupadd_i8vec2
Removing the GLK check solves the issue for GLK. I don't see a reason
on why implementing this restriction would actually break GLK, so
there's still more to investigate here since this bug may be affecting
ICL+, but let's apply the real GLK fix while we analyze and discuss
the other possible issues.
Fixes: 5847de6e9afe ("intel/compiler: don't use byte operands for src1
on ICL")
BSpec: 3017
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
(cherry picked from commit b57383a9445eae153fbf91fad8592d273b14e546)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd4b73ad380bdfba4207a989cb409f3bbf1f6437
Author: Daniel Schürmann <daniel at schuermann.dev>
Date: Thu Oct 31 17:33:35 2019 +0100
aco: fix accidential reordering of instructions when scheduling
Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
(cherry picked from commit efe737fc4f8f76f7d0b3bd8655eafc3196576a3d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8faeff399f7e0064e2b1472361d70ff7f7ed0f0
Author: Daniel Schürmann <daniel at schuermann.dev>
Date: Fri Nov 1 09:06:26 2019 +0100
aco: only use single-dword loads/stores for spilling
Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
(cherry picked from commit 5c7dcb15e0cc98fe9fa5fa25f320f2bdd71187c3)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d846243a02e5b2c39d75cf59b1a4009ffcc3058
Author: Daniel Schürmann <daniel at schuermann.dev>
Date: Thu Oct 31 13:25:44 2019 +0100
aco: fix immediate offset for spills if scratch is used
Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
(cherry picked from commit d97c0bdd5558e4e00ede38afac879606aff5f04b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc5357bf33632a4c25f9674fec874ba443b603c0
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Wed Oct 30 13:51:08 2019 +0200
anv: Properly handle host query reset of performance queries
The host query reset entry point didn't use the availability offset
for performance queries.
To fix this, reorder the availability of performance queries to match
other queries.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 2b5f30b1d9 ("anv: implement VK_INTEL_performance_query")
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit ee6fbb95a74d0dfc00fe77778828c73e6a1447fb)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5cee7ad873d437ac58b739d4b159c9a4352f99e5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Nov 3 23:50:38 2019 -0800
iris: Fix "Force Zero RTA Index Enable" setting again
In 2ca0d913ea8, we began updating cso_fb->layers to the actual layer
count, rather than 0. This fixed cases where we were setting "Force
Zero RTA Index Enable" even when doing layered rendering. Sadly, it
also broke the check entirely: cso_fb->layers is now 1 for non-layered
cases, but the Force Zero RTA Index check was still comparing for 0.
Fixes: 2ca0d913ea8 ("iris: Fix framebuffer layer count")
(cherry picked from commit fc7b7480867d6049ca12f87d9b6ab0d9ad55d59f)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=184d39301d9ef2b335867655b7ce27a351c0a945
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Fri Oct 25 13:48:38 2019 -0700
nir: correct use of identity check in python
Python has the identity operator `is`, and the equality operator `==`.
Using `is` with strings sometimes works in CPython due to optimizations
(they have some kind of cache), but it may not always work.
Fixes: 96c4b135e34d0804e41bfbc28fc1b5050c49d71e
("nir/algebraic: Don't put quotes around floating point literals")
Reviewed-by: Matt Turner <mattst88 at gmail.com>
(cherry picked from commit 717606f9f32af6540b68336e676fca9dd16f282a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bca129bb4c940ede3dbb493db4c0dbe5baee827
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Nov 1 09:34:12 2019 +0100
radv: fix compute pipeline keys when optimizations are disabled
If an app first creates a compute pipeline with
VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT set, then re-compile it
without that flag, the driver should re-compile the compute shader.
Otherwise, it will return the unoptimized one.
Fixes: ce188813bfe ("radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit 9ab27647ff5379e8095a70c23dd16792f074c8c7)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6daaf66f662ed5d3236c654721910506cc7f4c93
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Fri Nov 1 19:43:00 2019 +0200
mesa: check draw buffer completeness on glClearBufferfi/glClearBufferiv
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit 88d665830f27087cb2188e03b0b734acc144c593)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d21f802b56af984f2f2bfa9e40b84da550662b7
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Fri Nov 1 01:07:02 2019 +0100
radv: Close all unnecessary fds in secure compile.
The seccomp filter allows read/write, let us make sure nobody can
do anything with this.
Fixes: cff53da3748 "radv: enable secure compile support"
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
(cherry picked from commit 8efb8f55a617bebe5f33b9745cc22a2490828db8)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=090469173cc0168ec41d58f409f7a5af9540eda7
Author: Daniel Schürmann <daniel at schuermann.dev>
Date: Thu Oct 31 21:39:33 2019 +0100
docs/relnotes/new_features.txt: Add note about ACO
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59bc14186ecec006382f09b31eea7d75b0edf7c1
Author: Jan Zielinski <jan.zielinski at intel.com>
Date: Tue Oct 29 19:29:27 2019 +0100
gallium/swr: Fix depth values for blit scenario
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5032575b94916513b4b1a22c0967241b600f9a70
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Wed Oct 30 13:57:21 2019 +0100
zink: emit line-width when using polygon line-mode
When switching this to dynamic state, I forgot that this also needs to
be emitted when we use a polygon-mode set to lines.
Signed-off-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Fixes: 6d30abb4f14 ("zink: use dynamic state for line-width")
(cherry picked from commit b7674829a102b3e751e8d5fc9b29d9e9079dce4a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b981ca4d7ec2303a3dc063ae7a6899dc51ba55df
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date: Sat Oct 26 15:10:22 2019 -0400
pipe-loader: Build kmsro loader for with all kmsro targets
Build failure reported by i965 CI, triggered by building dynamic
pipeloaders with kmsro drivers (besides 'frost). At this point, there's
no reason to actually do that -- mesa CI didn't mind -- but let's not
break the build.
v2: Simplify script. Add extra dependencies for v3d.
Fixes: afb0d08cb0f ("pipe-loader: Default to kmsro if probe fails")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Reported-by: Clayton Craft <clayton.a.craft at intel.com>
Tested-by: Clayton Craft <clayton.a.craft at intel.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
(cherry picked from commit bf15318991e3111fa3d94a9d3d564c7c539b9f23)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3544a01121c36d08117193b4e392b6910fd749aa
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Wed Oct 30 14:37:45 2019 -0500
anv: Set the batch allocator for compute pipelines
Otherwise relocations just up and crash.
Fixes: a3153162a9b "anv: Delay allocation of relocation lists"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
(cherry picked from commit 9ef198c59a0cf003b4545e345d34b93d9e4c538b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb9d1ed2bd4450cb9177d0ff40d5fcb4634f3bfd
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Wed Oct 30 11:43:53 2019 -0500
anv/tests: Zero-initialize instances
Some of the tests were actually relying on some of those uninitialized
bits to be non-zero. In particular, a couple want use_softpin = true.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
(cherry picked from commit 9076e9f3751341063679eb227116060070549a37)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f8e0c715ef7d7ef5ae05696cfa7669273bb179d
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Fri Oct 25 15:42:22 2019 -0500
anv: Fix a potential BO handle leak
Fixes: 731c4adcf9b "anv/allocator: Add support for non-userptr"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
(cherry picked from commit bb257e1852473e3bc49bb9e0fe014741894f7bd0)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0104d8fefe9238aed4bb19113c4950ca226e1fd
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date: Tue Oct 29 19:45:48 2019 +0100
mesa: enable msaa in clear_with_quad if needed
If the DrawBuffer sample count is > 1 and msaa is enabled we must also
enable msaa when clearing it.
Fixes: ea5b7de138b ("radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1991
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Tested-by: Witold Baryluk <witold.baryluk at gmail.com>
(cherry picked from commit 8a723282e3f7a312ab0ca3aa9157e5b76ec182af)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb66ea7780fb68b7c19ab8fffa749614cd5da963
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Wed Oct 30 15:00:39 2019 +0100
radv: Fix disk_cache_get size argument.
Got some int->pointer warnings and 20 is not a valid pointer ....
Fixes: 2e3a635ee69 "radv: Add an early exit in the secure compile if we already have the cache entries."
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
(cherry picked from commit 6ced684e2743dec5b6db397fc45e464abf21b5e3)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=75886fafaad5af59f393e2eff589a637589b2ef2
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Thu Oct 31 02:36:23 2019 +0100
anv: Remove _mesa_locale_init/fini calls.
The resulting locale is not used for Vulkan, and it is not reference
counted, giving issues when multiple instances are created.
CC: 19.2 19.3 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit 3e86d553a470c484b6a2c60bc7866759ec21fea5)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3fd30921a2076866a940d8b7da85fe5f8474faf
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Thu Oct 31 02:35:51 2019 +0100
turnip: Remove _mesa_locale_init/fini calls.
The resulting locale is not used for Vulkan, and it is not reference
counted, giving issues when multiple instances are created.
CC: 19.2 19.3 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit 72f858fc07746eb1d7360b47636006202a075e84)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea886e49be9a9799d5dbae9d1f46d31499344b5e
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Thu Oct 31 02:33:46 2019 +0100
radv: Remove _mesa_locale_init/fini calls.
The resulting locale is not used for Vulkan, and it is not reference
counted, giving issues when multiple instances are created.
CC: 19.2 19.3 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit 344ba56b0f36e77c3d4a935717854f1bf8000a2e)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=307e5cc8fd7537d5faa0a2b6ca35076252fc9b15
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date: Wed Oct 30 14:28:01 2019 +0100
radeonsi: tell the shader disk cache what IR is used
Until 8bef4df196fbb the IR (TGSI or NIR) was used in disk_cache driver_flags.
This commit restores this features to avoid crashing when switching from
one IR to the other.
As radeonsi's default is TGSI, I used "driver_flags & 0x8000000 = 0" for TGSI
to keep the same driver_flags.
Fixes: 8bef4df196f ("radeonsi: add si_debug_options for convenient adding/removing of options")
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
(cherry picked from commit 2afeed301010917c4eae55dcd2544f9d329df934)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b8836cb23b50e66928591c100dcb9f301817e37
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Thu Oct 31 01:59:07 2019 +0100
android: aco: fix Lower to CSSA
Fixes the following building error:
external/mesa/src/amd/compiler/aco_spill.cpp:1768:
error: undefined reference to 'aco::lower_to_cssa(aco::Program*, aco::live&, radv_nir_compiler_options const*)'
Fixes: 0b8216b ("aco: Lower to CSSA")
Signed-off-by: Mauro Rossi <issor.oruam at gmail.com>
(cherry picked from commit d688e4166ca9c49a980a78ce91846fd7072df8fd)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=39e9739a3b283e8db3c74090728badbe3cfcab14
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Feb 15 11:35:28 2019 -0800
iris/gen11+: Move flush for render target change
When starting a BLORP operation, we do the BTI-change flush. However,
when ending it and transitioning back to regular drawing, we change the
render target again - without a set_framebuffer_state() call. We need
to do the BTI flush there too. BLORP flags IRIS_DIRTY_RENDER_BUFFER
now, which will cause the next draw to get the BTI flush again.
(explanation of fix by Ken)
Fixes: 2b956a093a1 ("iris: totally untested icelake support")
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit bb0c5c487e63e88acbb792f092dd8f392bad8540)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de705da8a6301cdf60a7739c89ff1e9100376164
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Feb 15 11:31:31 2019 -0800
iris: Add IRIS_DIRTY_RENDER_BUFFER state flag
Fixes: 2b956a093a1 ("iris: totally untested icelake support")
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit a2c3c65a31de90fdb55f76f2894860dfbafe2043)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=640747a298072c7428edf5fd4d268e17368b331f
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Oct 29 12:18:16 2019 -0700
intel/compiler: Report the number of non-spill/fill SEND messages on vec4 too
This make shader-db's report.py work on Haswell and earlier platforms.
The problem is that the script would detect the "sends" output for
scalar shaders and expect in in vec4 shaders too. When it didn't find
it, the script would fail with:
Traceback (most recent call last):
File "./report.py", line 351, in <module>
main()
File "./report.py", line 182, in main
before_count = before[p][m]
KeyError: 'sends'
Fixes: f192741ddd8 ("intel/compiler: Report the number of non-spill/fill SEND messages")
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit 7b3f38ef69769f1d2bc022186b404885396b1136)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9df476344031e31c5cff050cb647990ed999fe32
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Wed Oct 30 21:58:42 2019 +0100
radv: Fix timeout handling in syncobj wait.
libdrm returns -errno instead of directly the ioctl ret of -1.
Fixes: 1c3cda7d277 "radv: Add syncobj signal/reset/wait to winsys."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit ec770085c270cb167c02f299f6985744682933b1)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b1b7afb5c2d145166908cae77df6178426bb31f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Oct 14 02:40:11 2019 -0400
nv50/ir: mark STORE destination inputs as used
Observed an issue when looking at the code generatedy by the
image-vertex-attrib-input-output piglit test. Even though the test
itself worked fine (due to TIC 0 being used for the image), this needs
to be fixed.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit 1b9d1e13d8e14c348f6d6c8fab5f31e8768a1371)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=084926926c678a8b6e10eb6f99f02a89c9f11a6b
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Oct 31 00:03:30 2019 +0200
intel/dev: set default num_eu_per_subslice on gen12
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 8125d7960b ("intel/dev: Add preliminary device info for Tigerlake")
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit e02c181bfdc554f298f861bb39d20f0bfd7c2dca)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1beee9dd9f6d885a286e638b0da977feed206cfc
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Feb 3 23:25:07 2019 -0500
gm107/ir: fix loading z offset for layered 3d image bindings
Unfortuantely we don't know if a particular load is a real 2d image (as
would be a cube face or 2d array element), or a layer of a 3d image.
Since we pass in the TIC reference, the instruction's type has to match
what's in the TIC (experimentally). In order to properly support
bindless images, this also can't be done by looking at the current
bindings and generating appropriate code.
As a result all plain 2d loads are converted into a pair of 2d/3d loads,
with appropriate predicates to ensure only one of those actually
executes, and the values are all merged in.
This goes somewhat against the current flow, so for GM107 we do the OOB
handling directly in the surface processing logic. Perhaps the other
gens should do something similar, but that is left to another change.
This fixes dEQP tests like image_load_store.3d.*_single_layer and GL-CTS
tests like shader_image_load_store.non-layered_binding without breaking
anything else.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "20.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 869e32593a9096b845dd6106f8f86e1c41fac968)
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