Mesa (master): freedreno/ir3: fixup cat3 32b vs 16b
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Sat Apr 4 00:24:57 UTC 2020
Module: Mesa
Branch: master
Commit: c2d0cc8b8d5bd2f3b194642fd0187283da51d4ae
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2d0cc8b8d5bd2f3b194642fd0187283da51d4ae
Author: Rob Clark <robdclark at chromium.org>
Date: Mon Mar 16 07:05:01 2020 -0700
freedreno/ir3: fixup cat3 32b vs 16b
These should be keyed on src arg type.
Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
---
src/freedreno/ir3/ir3_ra.c | 48 +++++++++++++++-------------------------------
1 file changed, 15 insertions(+), 33 deletions(-)
diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c
index a630202a3e2..40ea78609ce 100644
--- a/src/freedreno/ir3/ir3_ra.c
+++ b/src/freedreno/ir3/ir3_ra.c
@@ -1082,39 +1082,6 @@ static void fixup_half_instr_dst(struct ir3_instruction *instr)
case 1: /* move instructions */
instr->cat1.dst_type = half_type(instr->cat1.dst_type);
break;
- case 3:
- switch (instr->opc) {
- case OPC_MAD_F32:
- /* Available for that dest is half and srcs are full.
- * eg. mad.f32 hr0, r0.x, r0.y, r0.z
- */
- if (instr->regs[1]->flags & IR3_REG_HALF)
- instr->opc = OPC_MAD_F16;
- break;
- case OPC_SEL_B32:
- instr->opc = OPC_SEL_B16;
- break;
- case OPC_SEL_S32:
- instr->opc = OPC_SEL_S16;
- break;
- case OPC_SEL_F32:
- instr->opc = OPC_SEL_F16;
- break;
- case OPC_SAD_S32:
- instr->opc = OPC_SAD_S16;
- break;
- /* instructions may already be fixed up: */
- case OPC_MAD_F16:
- case OPC_SEL_B16:
- case OPC_SEL_S16:
- case OPC_SEL_F16:
- case OPC_SAD_S16:
- break;
- default:
- assert(0);
- break;
- }
- break;
case 4:
switch (instr->opc) {
case OPC_RSQ:
@@ -1142,6 +1109,21 @@ static void fixup_half_instr_src(struct ir3_instruction *instr)
case OPC_MOV:
instr->cat1.src_type = half_type(instr->cat1.src_type);
break;
+ case OPC_MAD_F32:
+ instr->opc = OPC_MAD_F16;
+ break;
+ case OPC_SEL_B32:
+ instr->opc = OPC_SEL_B16;
+ break;
+ case OPC_SEL_S32:
+ instr->opc = OPC_SEL_S16;
+ break;
+ case OPC_SEL_F32:
+ instr->opc = OPC_SEL_F16;
+ break;
+ case OPC_SAD_S32:
+ instr->opc = OPC_SAD_S16;
+ break;
default:
break;
}
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