Mesa (master): iris: Fix headerless sampler messages in compute shaders with preemption

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Module: Mesa
Branch: master
Commit: 3fed1c75ef4d165a3c96f3a9ac0295268c16c6be
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3fed1c75ef4d165a3c96f3a9ac0295268c16c6be

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Aug 18 13:56:22 2020 -0700

iris: Fix headerless sampler messages in compute shaders with preemption

We were failing to set the "Headerless Message for Preemptable Contexts"
bit in SAMPLER_MODE in the compute context.  Other drivers use a single
hardware context, so setting it on the render engine was sufficient to
flip it in both pipelines.  But iris uses a separate hardware context
for compute, so we were only getting these set for the render context.

Thanks to Jason Ekstrand for catching this bug.

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6380>

---

 src/gallium/drivers/iris/iris_state.c | 43 ++++++++++++++++++++++++-----------
 1 file changed, 30 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index e9f391d5a5c..7d9ac074988 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -905,6 +905,32 @@ static void
 init_aux_map_state(struct iris_batch *batch);
 #endif
 
+/**
+ * Upload initial GPU state for any kind of context.
+ *
+ * These need to happen for both render and compute.
+ */
+static void
+iris_init_common_context(struct iris_batch *batch)
+{
+#if GEN_GEN == 11
+   uint32_t reg_val;
+
+   iris_pack_state(GENX(SAMPLER_MODE), &reg_val, reg) {
+      reg.HeaderlessMessageforPreemptableContexts = 1;
+      reg.HeaderlessMessageforPreemptableContextsMask = 1;
+   }
+   iris_emit_lri(batch, SAMPLER_MODE, reg_val);
+
+   /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
+   iris_pack_state(GENX(HALF_SLICE_CHICKEN7), &reg_val, reg) {
+      reg.EnabledTexelOffsetPrecisionFix = 1;
+      reg.EnabledTexelOffsetPrecisionFixMask = 1;
+   }
+   iris_emit_lri(batch, HALF_SLICE_CHICKEN7, reg_val);
+#endif
+}
+
 /**
  * Upload the initial GPU state for a render context.
  *
@@ -925,6 +951,8 @@ iris_init_render_context(struct iris_batch *batch)
 
    init_state_base_address(batch);
 
+   iris_init_common_context(batch);
+
 #if GEN_GEN >= 9
    iris_pack_state(GENX(CS_DEBUG_MODE2), &reg_val, reg) {
       reg.CONSTANT_BUFFERAddressOffsetDisable = true;
@@ -961,19 +989,6 @@ iris_init_render_context(struct iris_batch *batch)
    }
    iris_emit_lri(batch, TCCNTLREG, reg_val);
 
-   iris_pack_state(GENX(SAMPLER_MODE), &reg_val, reg) {
-      reg.HeaderlessMessageforPreemptableContexts = 1;
-      reg.HeaderlessMessageforPreemptableContextsMask = 1;
-   }
-   iris_emit_lri(batch, SAMPLER_MODE, reg_val);
-
-   /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
-   iris_pack_state(GENX(HALF_SLICE_CHICKEN7), &reg_val, reg) {
-      reg.EnabledTexelOffsetPrecisionFix = 1;
-      reg.EnabledTexelOffsetPrecisionFixMask = 1;
-   }
-   iris_emit_lri(batch, HALF_SLICE_CHICKEN7, reg_val);
-
    /* Hardware specification recommends disabling repacking for the
     * compatibility with decompression mechanism in display controller.
     */
@@ -1053,6 +1068,8 @@ iris_init_compute_context(struct iris_batch *batch)
 
    init_state_base_address(batch);
 
+   iris_init_common_context(batch);
+
 #if GEN_GEN == 12
    emit_pipeline_select(batch, GPGPU);
 #endif