Mesa (master): intel/blorp: Fill out all the dwords of MI_ATOMIC

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Module: Mesa
Branch: master
Commit: d7ff137445b9bfd0cf15d176d0d152d16634559f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7ff137445b9bfd0cf15d176d0d152d16634559f

Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Fri Jan 10 15:30:02 2020 -0600

intel/blorp: Fill out all the dwords of MI_ATOMIC

This makes us valgrind clean again.

Fixes: 9175c7058efb "intel/blorp: Make blorp update the clear color..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366>

---

 src/intel/blorp/blorp_genX_exec.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 348970a491b..9db829c30f2 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1792,7 +1792,9 @@ blorp_update_clear_color(struct blorp_batch *batch,
                                  .MemoryAddress = clear_addr);
       /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
       dw[2] = info->clear_color.u32[0];
+      dw[3] = 0;
       dw[4] = info->clear_color.u32[1];
+      dw[5] = 0;
 
       clear_addr.offset += 8;
       dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords,
@@ -1804,7 +1806,9 @@ blorp_update_clear_color(struct blorp_batch *batch,
                                  .MemoryAddress = clear_addr);
       /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
       dw[2] = info->clear_color.u32[2];
+      dw[3] = 0;
       dw[4] = info->clear_color.u32[3];
+      dw[5] = 0;
 
       blorp_emit(batch, GENX(PIPE_CONTROL), pipe) {
          pipe.StateCacheInvalidationEnable = true;