Mesa (master): freedreno/ir3: Account for driver params in UBO max const upload.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 486b89430795cf12c0fe027fa070b75262337a18
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=486b89430795cf12c0fe027fa070b75262337a18

Author: Eric Anholt <eric at anholt.net>
Date:   Fri May 29 16:31:43 2020 -0700

freedreno/ir3: Account for driver params in UBO max const upload.

The const state setup needs to be able to push its driver params, so
account for them in the analyze_ubo_ranges.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5273>

---

 src/freedreno/ir3/ir3_nir.c                    | 17 +++++++++++------
 src/freedreno/ir3/ir3_nir.h                    |  3 +++
 src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c | 13 ++++++++++++-
 3 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index ac07224b8e1..364ebf3057a 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -32,8 +32,6 @@
 #include "ir3_compiler.h"
 #include "ir3_shader.h"
 
-static void ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir);
-
 static const nir_shader_compiler_options options = {
 		.lower_fpow = true,
 		.lower_scmp = true,
@@ -369,7 +367,7 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 	 * analysis.
 	 */
 	if (!key) {
-		ir3_setup_const_state(shader, s);
+		ir3_setup_const_state(shader, s, &shader->const_state);
 	}
 }
 
@@ -449,11 +447,16 @@ ir3_nir_scan_driver_consts(nir_shader *shader,
 	}
 }
 
-static void
-ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
+/* Sets up the non-variant-dependent constant state for the ir3_shader.  Note
+ * that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
+ * maximum number of driver params that would eventually be used, to leave
+ * space for this function to allocate the driver params.
+ */
+void
+ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir,
+	struct ir3_const_state *const_state)
 {
 	struct ir3_compiler *compiler = shader->compiler;
-	struct ir3_const_state *const_state = &shader->const_state;
 
 	memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
 
@@ -530,4 +533,6 @@ ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
 	}
 
 	const_state->offsets.immediate = constoff;
+
+	assert(constoff <= compiler->max_const);
 }
diff --git a/src/freedreno/ir3/ir3_nir.h b/src/freedreno/ir3/ir3_nir.h
index bd29da7c6c6..39930a40778 100644
--- a/src/freedreno/ir3/ir3_nir.h
+++ b/src/freedreno/ir3/ir3_nir.h
@@ -56,6 +56,9 @@ bool ir3_key_lowers_nir(const struct ir3_shader_key *key);
 void ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 		const struct ir3_shader_key *key);
 
+void ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir,
+		struct ir3_const_state *const_state);
+
 bool ir3_nir_analyze_ubo_ranges(nir_shader *nir, struct ir3_shader *shader);
 
 nir_ssa_def *
diff --git a/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c b/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c
index a4733cdb2ef..d7dd9b912c8 100644
--- a/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c
+++ b/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c
@@ -331,7 +331,18 @@ ir3_nir_analyze_ubo_ranges(nir_shader *nir, struct ir3_shader *shader)
 	 * dynamically accessed ranges separately and upload static rangtes
 	 * first.
 	 */
-	const uint32_t max_upload = shader->compiler->max_const * 16;
+
+	/* Limit our uploads to the amount of constant buffer space available in
+	 * the hardware, minus what the shader compiler may need for various
+	 * driver params.  We do this UBO-to-push-constant before the real
+	 * allocation of the driver params' const space, because UBO pointers can
+	 * be driver params but this pass usually eliminatings them.
+	 */
+	struct ir3_const_state worst_case_const_state = { };
+	ir3_setup_const_state(shader, nir, &worst_case_const_state);
+	const uint32_t max_upload = (shader->compiler->max_const -
+			worst_case_const_state.offsets.immediate) * 16;
+
 	uint32_t offset = shader->const_state.num_reserved_user_consts * 16;
 	state->num_enabled = ARRAY_SIZE(state->range);
 	for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {