Mesa (master): intel/tools: Require explicit regions/types for special regs

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Module: Mesa
Branch: master
Commit: cc6fc963f02f727101f95d086065f332bd89e9e7
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc6fc963f02f727101f95d086065f332bd89e9e7

Author: Matt Turner <mattst88 at gmail.com>
Date:   Tue Jun 16 16:54:07 2020 -0700

intel/tools: Require explicit regions/types for special regs

The docs say that these registers should  only be read with a certain
type, and I'm inclined to believe that the hardware behaves that way,
but it makes the assembler a little more confusing and also confuses the
user of the assembler that some operands don't take types or regions.

Just always requiring regions and types seems like the sensible thing.

Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>

---

 src/intel/tools/i965_gram.y | 38 ++++++++++----------------------------
 1 file changed, 10 insertions(+), 28 deletions(-)

diff --git a/src/intel/tools/i965_gram.y b/src/intel/tools/i965_gram.y
index 55eaabc154d..e236113771c 100644
--- a/src/intel/tools/i965_gram.y
+++ b/src/intel/tools/i965_gram.y
@@ -470,7 +470,6 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
 
 /* dst operand */
 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
-%type <reg> dstoperandex_ud_typed
 %type <integer> dstregion
 
 %type <integer> saturate relativelocation rellocation
@@ -479,7 +478,7 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
 /* src operand */
 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
-%type <reg> srcarcoperandex_ud_typed srcimmtype indirectgenreg indirectregion
+%type <reg> srcimmtype indirectgenreg indirectregion
 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
 %type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
 
@@ -1447,12 +1446,6 @@ dstoperandex:
 		$$.writemask = $3.writemask;
 		$$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
 	}
-	| dstoperandex_ud_typed
-	{
-		$$ = $1;
-		$$.hstride = 1;
-		$$.type = BRW_REGISTER_TYPE_UD;
-	}
 	/* BSpec says "When the conditional modifier is present, updates
 	 * to the selected flag register also occur. In this case, the
 	 * register region fields of the ‘null’ operand are valid."
@@ -1478,18 +1471,15 @@ dstoperandex:
 	}
 	;
 
-dstoperandex_ud_typed:
-	controlreg
-	| ipreg
-	| channelenablereg
-	| performancereg
-	;
-
 dstoperandex_typed:
 	accreg
-	| flagreg
 	| addrreg
+	| channelenablereg
+	| controlreg
+	| flagreg
+	| ipreg
 	| maskreg
+	| performancereg
 	| statereg
 	;
 
@@ -1631,10 +1621,6 @@ srcarcoperandex:
 			     BRW_SWIZZLE_NOOP,
 			     WRITEMASK_XYZW);
 	}
-	| srcarcoperandex_ud_typed
-	{
-		$$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UD);
-	}
 	| nullreg region srctype
 	{
 		$$ = set_direct_src_operand(&$1, $3.type);
@@ -1648,15 +1634,11 @@ srcarcoperandex:
 	}
 	;
 
-srcarcoperandex_ud_typed:
-	controlreg
-	| statereg
-	| ipreg
-	| channelenablereg
-	;
-
 srcarcoperandex_typed:
-	flagreg
+	channelenablereg
+	| controlreg
+	| flagreg
+	| ipreg
 	| maskreg
 	| statereg
 	;