Mesa (master): intel/tools: Add assembler tests for the cr0 register
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Fri Jun 19 02:24:09 UTC 2020
Module: Mesa
Branch: master
Commit: 1f871062764f6c3fdfa5c1ad4b7db525c5c6f42b
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f871062764f6c3fdfa5c1ad4b7db525c5c6f42b
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Jun 16 17:10:38 2020 -0700
intel/tools: Add assembler tests for the cr0 register
Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
---
src/intel/tools/tests/gen11/cr0.asm | 7 +++++++
src/intel/tools/tests/gen11/cr0.expected | 7 +++++++
src/intel/tools/tests/gen8/cr0.asm | 14 ++++++++++++++
src/intel/tools/tests/gen8/cr0.expected | 14 ++++++++++++++
src/intel/tools/tests/gen9/cr0.asm | 14 ++++++++++++++
src/intel/tools/tests/gen9/cr0.expected | 14 ++++++++++++++
6 files changed, 70 insertions(+)
diff --git a/src/intel/tools/tests/gen11/cr0.asm b/src/intel/tools/tests/gen11/cr0.asm
new file mode 100644
index 00000000000..a6213bb0f93
--- /dev/null
+++ b/src/intel/tools/tests/gen11/cr0.asm
@@ -0,0 +1,7 @@
+and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000080UD { align1 1N switch };
diff --git a/src/intel/tools/tests/gen11/cr0.expected b/src/intel/tools/tests/gen11/cr0.expected
new file mode 100644
index 00000000000..60e24ef73ef
--- /dev/null
+++ b/src/intel/tools/tests/gen11/cr0.expected
@@ -0,0 +1,7 @@
+05 80 00 00 00 00 00 30 00 10 00 06 7f fb ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 7f ff ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 cf ff ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 ff fb ff ff
+06 80 00 00 00 00 00 30 00 10 00 06 00 04 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 30 00 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 80 00 00 00
diff --git a/src/intel/tools/tests/gen8/cr0.asm b/src/intel/tools/tests/gen8/cr0.asm
new file mode 100644
index 00000000000..d5b67ca9cf1
--- /dev/null
+++ b/src/intel/tools/tests/gen8/cr0.asm
@@ -0,0 +1,14 @@
+and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000040UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000440UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000080UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000480UD { align1 1N switch };
diff --git a/src/intel/tools/tests/gen8/cr0.expected b/src/intel/tools/tests/gen8/cr0.expected
new file mode 100644
index 00000000000..ccf8a886035
--- /dev/null
+++ b/src/intel/tools/tests/gen8/cr0.expected
@@ -0,0 +1,14 @@
+05 80 00 00 00 00 00 30 00 10 00 06 3f fb ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 3f ff ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 7f fb ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 7f ff ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 bf fb ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 bf ff ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 cf ff ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 ff fb ff ff
+06 80 00 00 00 00 00 30 00 10 00 06 00 04 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 30 00 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 40 00 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 40 04 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 80 00 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 80 04 00 00
diff --git a/src/intel/tools/tests/gen9/cr0.asm b/src/intel/tools/tests/gen9/cr0.asm
new file mode 100644
index 00000000000..d5b67ca9cf1
--- /dev/null
+++ b/src/intel/tools/tests/gen9/cr0.asm
@@ -0,0 +1,14 @@
+and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
+and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000040UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000440UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000080UD { align1 1N switch };
+or(1) cr0<1>UD cr0<0,1,0>UD 0x00000480UD { align1 1N switch };
diff --git a/src/intel/tools/tests/gen9/cr0.expected b/src/intel/tools/tests/gen9/cr0.expected
new file mode 100644
index 00000000000..ccf8a886035
--- /dev/null
+++ b/src/intel/tools/tests/gen9/cr0.expected
@@ -0,0 +1,14 @@
+05 80 00 00 00 00 00 30 00 10 00 06 3f fb ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 3f ff ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 7f fb ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 7f ff ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 bf fb ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 bf ff ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 cf ff ff ff
+05 80 00 00 00 00 00 30 00 10 00 06 ff fb ff ff
+06 80 00 00 00 00 00 30 00 10 00 06 00 04 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 30 00 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 40 00 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 40 04 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 80 00 00 00
+06 80 00 00 00 00 00 30 00 10 00 06 80 04 00 00
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