Mesa (master): radv: replace == GFX10 with >= GFX10 where it's needed

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Module: Mesa
Branch: master
Commit: 3c28438094b8345bc0797e02af728ca41049d4bb
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c28438094b8345bc0797e02af728ca41049d4bb

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Mon Jun  8 18:38:57 2020 +0200

radv: replace == GFX10 with >= GFX10 where it's needed

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>

---

 src/amd/vulkan/radv_image.c       | 2 +-
 src/amd/vulkan/radv_nir_to_llvm.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index e4bbbab4ca2..8c65eb6bc37 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -98,7 +98,7 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device,
 	if (pCreateInfo->samples >= 2 &&
 	    (format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
 	     (format == VK_FORMAT_D32_SFLOAT &&
-	      device->physical_device->rad_info.chip_class == GFX10)))
+	      device->physical_device->rad_info.chip_class >= GFX10)))
 		return false;
 
 	/* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index e8ad6d83df3..6ad327b2003 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1271,7 +1271,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
 		 * access are detected. Only GFX6 and GFX10 are affected.
 		 */
 		bool unaligned_vertex_fetches = false;
-		if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class == GFX10) &&
+		if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class >= GFX10) &&
 		    vtx_info->chan_format != data_format &&
 		    ((attrib_offset % vtx_info->element_size) ||
 		     (attrib_stride % vtx_info->element_size)))
@@ -1282,7 +1282,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
 			LLVMValueRef values[4];
 
 			assert(ctx->ac.chip_class == GFX6 ||
-			       ctx->ac.chip_class == GFX10);
+			       ctx->ac.chip_class >= GFX10);
 
 			for (unsigned chan  = 0; chan < num_channels; chan++) {
 				unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size;