Mesa (master): freedreno/registers: a6xx depth bounds test registers

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Module: Mesa
Branch: master
Commit: a9d866910c59a2e9e0c001b2d5f337205d8c3c1f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9d866910c59a2e9e0c001b2d5f337205d8c3c1f

Author: Jonathan Marek <jonathan at marek.ca>
Date:   Tue Jun 23 18:44:42 2020 -0400

freedreno/registers: a6xx depth bounds test registers

Signed-off-by: Jonathan Marek <jonathan at marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5628>

---

 src/freedreno/registers/a6xx.xml              | 12 +++++++-----
 src/freedreno/vulkan/tu_cmd_buffer.c          |  4 ++--
 src/gallium/drivers/freedreno/a6xx/fd6_emit.c |  4 ++--
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index 9699caefb8d..32c280370b5 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -2300,8 +2300,12 @@ to upconvert to 32b float internally?
 		<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
 		<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
 		<bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
-		<doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
+		<doc>
+		Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
+		also set when Z_BOUNDS_ENABLE is set
+		</doc>
 		<bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
+		<bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
 	</reg32>
 	<!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
 	<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
@@ -2319,10 +2323,8 @@ to upconvert to 32b float internally?
 	<reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress"/>
 	<reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/>
 
-	<!-- always 0x0 ? -->
-	<reg32 offset="0x8878" name="RB_UNKNOWN_8878"/>
-	<!-- always 0x0 ? -->
-	<reg32 offset="0x8879" name="RB_UNKNOWN_8879"/>
+	<reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float"/>
+	<reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float"/>
 
 	<reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
 		<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index c98834b6977..4926ef42e8c 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -971,8 +971,8 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
-   tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
-   tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
+   tu_cs_emit_write_reg(cs, REG_A6XX_RB_Z_BOUNDS_MIN, 0);
+   tu_cs_emit_write_reg(cs, REG_A6XX_RB_Z_BOUNDS_MAX, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
 
    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index ed6dcf3239e..a55bb053e04 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -1204,8 +1204,8 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
 	WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0xa2);
 	WRITE(REG_A6XX_RB_SAMPLE_CONFIG, 0);
 	WRITE(REG_A6XX_GRAS_SAMPLE_CONFIG, 0);
-	WRITE(REG_A6XX_RB_UNKNOWN_8878, 0);
-	WRITE(REG_A6XX_RB_UNKNOWN_8879, 0);
+	WRITE(REG_A6XX_RB_Z_BOUNDS_MIN, 0);
+	WRITE(REG_A6XX_RB_Z_BOUNDS_MAX, 0);
 	WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
 
 	emit_marker6(ring, 7);