Mesa (master): turnip: implement depthBounds

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Module: Mesa
Branch: master
Commit: 01e2893cba4dd0f3ef98020ef0707510ce2cfde8
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=01e2893cba4dd0f3ef98020ef0707510ce2cfde8

Author: Jonathan Marek <jonathan at marek.ca>
Date:   Tue Jun 23 18:45:32 2020 -0400

turnip: implement depthBounds

Signed-off-by: Jonathan Marek <jonathan at marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5628>

---

 src/freedreno/vulkan/tu_cmd_buffer.c |  8 ++++++--
 src/freedreno/vulkan/tu_device.c     |  2 +-
 src/freedreno/vulkan/tu_pipeline.c   | 13 ++++++++++---
 3 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index 4926ef42e8c..6b58a154c44 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -971,8 +971,6 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
-   tu_cs_emit_write_reg(cs, REG_A6XX_RB_Z_BOUNDS_MIN, 0);
-   tu_cs_emit_write_reg(cs, REG_A6XX_RB_Z_BOUNDS_MAX, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
 
    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
@@ -2326,6 +2324,12 @@ tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
                      float minDepthBounds,
                      float maxDepthBounds)
 {
+   TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+   struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3);
+
+   tu_cs_emit_regs(&cs,
+                   A6XX_RB_Z_BOUNDS_MIN(minDepthBounds),
+                   A6XX_RB_Z_BOUNDS_MAX(maxDepthBounds));
 }
 
 static void
diff --git a/src/freedreno/vulkan/tu_device.c b/src/freedreno/vulkan/tu_device.c
index ee8120a948d..63d33e531b4 100644
--- a/src/freedreno/vulkan/tu_device.c
+++ b/src/freedreno/vulkan/tu_device.c
@@ -595,7 +595,7 @@ tu_GetPhysicalDeviceFeatures(VkPhysicalDevice physicalDevice,
       .depthClamp = true,
       .depthBiasClamp = false,
       .fillModeNonSolid = false,
-      .depthBounds = false,
+      .depthBounds = true,
       .wideLines = false,
       .largePoints = false,
       .alphaToOne = true,
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 58cbd3c3cca..30c5361c56d 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -1629,14 +1629,12 @@ tu6_emit_depth_control(struct tu_cs *cs,
                        const VkPipelineDepthStencilStateCreateInfo *ds_info,
                        const VkPipelineRasterizationStateCreateInfo *rast_info)
 {
-   assert(!ds_info->depthBoundsTestEnable);
-
    uint32_t rb_depth_cntl = 0;
    if (ds_info->depthTestEnable) {
       rb_depth_cntl |=
          A6XX_RB_DEPTH_CNTL_Z_ENABLE |
          A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
-         A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
+         A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
 
       if (rast_info->depthClampEnable)
          rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
@@ -1645,6 +1643,9 @@ tu6_emit_depth_control(struct tu_cs *cs,
          rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
    }
 
+   if (ds_info->depthBoundsTestEnable)
+         rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
+
    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
    tu_cs_emit(cs, rb_depth_cntl);
 }
@@ -2245,6 +2246,12 @@ tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
 
    pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
 
+   if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) {
+      tu_cs_emit_regs(&cs,
+                      A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
+                      A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
+   }
+
    if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
       tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
                                                .bfmask = ds_info->back.compareMask & 0xff));