Mesa (master): freedreno/a6xx+ir3: stop generating pointless binning shaders

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 83b97bf161f50371a09fdc02b3ca045671469b09
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=83b97bf161f50371a09fdc02b3ca045671469b09

Author: Rob Clark <robdclark at chromium.org>
Date:   Sat Jun 20 12:39:14 2020 -0700

freedreno/a6xx+ir3: stop generating pointless binning shaders

Currently we always do sysmem if there is tess.  And for GS, the binning
pass VS ends up identical to the draw pass VS, so no point in compiling
it twice.  (For GS what we should do someday is generate a binning pass
GS, and possibly if we can do cross-stage linking opts, an optimized
binning pass VS, but the required outputs would somehow have to end up
in the shader variant key.)

Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>

---

 src/freedreno/ir3/ir3_shader.h                   | 11 +++++++++++
 src/freedreno/vulkan/tu_pipeline.c               |  3 ++-
 src/gallium/drivers/freedreno/a6xx/fd6_program.c |  5 +----
 src/gallium/drivers/freedreno/ir3/ir3_cache.c    | 15 +++++++--------
 4 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h
index cbbdce767ee..2ccc9a86cd3 100644
--- a/src/freedreno/ir3/ir3_shader.h
+++ b/src/freedreno/ir3/ir3_shader.h
@@ -643,6 +643,17 @@ ir3_shader_stage(struct ir3_shader_variant *v)
 	}
 }
 
+/* Currently we do not do binning for tess.  And for GS there is no
+ * cross-stage VS+GS optimization, so the full VS+GS is used in
+ * the binning pass.
+ */
+static inline bool
+ir3_has_binning_vs(const struct ir3_shader_key *key)
+{
+	if (key->tessellation || key->has_gs)
+		return false;
+	return true;
+}
 
 /**
  * Represents a shader at the API level, before state-specific variants are
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 54d011b002a..64a92008af2 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -2001,7 +2001,8 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
    const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
    struct ir3_shader_variant *variant;
 
-   if (vs->ir3_shader->stream_output.num_outputs) {
+   if (vs->ir3_shader->stream_output.num_outputs ||
+       !ir3_has_binning_vs(&key)) {
       variant = builder->variants[MESA_SHADER_VERTEX];
    } else {
       bool created;
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index dbf145359df..5b5d9b56420 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -228,10 +228,7 @@ setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *stat
 	OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 	OUT_RING(ring, 0xff);        /* XXX */
 
-	if (state->ds)
-		debug_assert(state->ds->constlen >= state->bs->constlen);
-	else
-		debug_assert(state->vs->constlen >= state->bs->constlen);
+	debug_assert(state->vs->constlen >= state->bs->constlen);
 
 	OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
 	OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(state->vs->constlen) |
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cache.c b/src/gallium/drivers/freedreno/ir3/ir3_cache.c
index 5f6bb20fe8b..606e610be79 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cache.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cache.c
@@ -132,17 +132,16 @@ ir3_cache_lookup(struct ir3_cache *cache, const struct ir3_cache_key *key,
 		}
 	}
 
-	/* For tessellation, the binning shader is derived from the DS. */
 	struct ir3_shader_variant *bs;
-	if (key->ds) {
-		shader_key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_TESS_EVAL));
-		bs = ir3_shader_variant(key->ds, shader_key, true, debug);
-	} else {
+
+	if (ir3_has_binning_vs(&key->key)) {
 		shader_key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_VERTEX));
-		bs = ir3_shader_variant(key->vs, shader_key, true, debug);
+		bs = ir3_shader_variant(key->vs, key->key, true, debug);
+		if (!bs)
+			return NULL;
+	} else {
+		bs = variants[MESA_SHADER_VERTEX];
 	}
-	if (!bs)
-		return NULL;
 
 	struct ir3_program_state *state =
 		cache->funcs->create_state(cache->data, bs,