Mesa (master): tgsi_to_nir: translate non-vec4 image stores correctly

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Module: Mesa
Branch: master
Commit: d5109741f372173d6e13bdb6fff06c75def19439
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5109741f372173d6e13bdb6fff06c75def19439

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue May  5 12:44:54 2020 -0400

tgsi_to_nir: translate non-vec4 image stores correctly

set the correct number of components for src data and the intrinsic

Reviewed-by: Rob Clark <robdclark at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4908>

---

 src/gallium/auxiliary/nir/tgsi_to_nir.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 34ececa17a3..2865697482e 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -1846,12 +1846,15 @@ ttn_mem(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
          instr->src[3] = nir_src_for_ssa(nir_imm_int(b, 0)); /* LOD */
       }
 
+      unsigned num_components = util_last_bit(tgsi_inst->Dst[0].Register.WriteMask);
+
       if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
-         instr->src[3] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W), 4));
+         instr->src[3] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
+                                                     num_components));
          instr->src[4] = nir_src_for_ssa(nir_imm_int(b, 0)); /* LOD */
       }
 
-      instr->num_components = 4;
+      instr->num_components = num_components;
    } else {
       unreachable("unexpected file");
    }