Mesa (master): aco: validate 8-bit/16-bit VGPR operands for readfirstlane/readlane/writelane
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Thu May 21 15:15:03 UTC 2020
Module: Mesa
Branch: master
Commit: af7e2c61335640b4b23bdf907ea9ec94c89c218b
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=af7e2c61335640b4b23bdf907ea9ec94c89c218b
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Apr 8 08:53:47 2020 +0200
aco: validate 8-bit/16-bit VGPR operands for readfirstlane/readlane/writelane
I would expect it to just work as intended and other solutions,
like v_and_b32 to make sure the upper bits are 0, might have some
overhead.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
---
src/amd/compiler/aco_validate.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp
index e101d20068c..65ca2b45065 100644
--- a/src/amd/compiler/aco_validate.cpp
+++ b/src/amd/compiler/aco_validate.cpp
@@ -229,7 +229,7 @@ void validate(Program* program, FILE * output)
instr->opcode == aco_opcode::v_writelane_b32 ||
instr->opcode == aco_opcode::v_writelane_b32_e64) {
check(!op.isLiteral(), "No literal allowed on VALU instruction", instr.get());
- check(i == 1 || (op.isTemp() && op.regClass() == v1), "Wrong Operand type for VALU instruction", instr.get());
+ check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4), "Wrong Operand type for VALU instruction", instr.get());
continue;
}
if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
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