Mesa (master): util/threaded_context: use driver's buffer alignment for staging transfers

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Module: Mesa
Branch: master
Commit: 092186d9857e81f5f4c4f3c3a8820cb2d1a57b9a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=092186d9857e81f5f4c4f3c3a8820cb2d1a57b9a

Author: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Date:   Wed Nov  4 17:48:21 2020 -0500

util/threaded_context: use driver's buffer alignment for staging transfers

this coincidentally worked because radeonsi has a hardcoded value of 64, but
other drivers do not use this value and then things are subtly broken

Reviewed-by: Adam Jackson <ajax at redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7452>

---

 src/gallium/auxiliary/util/u_threaded_context.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/util/u_threaded_context.c b/src/gallium/auxiliary/util/u_threaded_context.c
index 093f9d594d5..1eaff77724e 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.c
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -1566,7 +1566,8 @@ tc_transfer_map(struct pipe_context *_pipe,
 
          u_upload_alloc(tc->base.stream_uploader, 0,
                         box->width + (box->x % tc->map_buffer_alignment),
-                        64, &ttrans->offset, &ttrans->staging, (void**)&map);
+                        tc->map_buffer_alignment, &ttrans->offset,
+                        &ttrans->staging, (void**)&map);
          if (!map) {
             slab_free(&tc->pool_transfers, ttrans);
             return NULL;