Mesa (master): freedreno/a6xx: add support for ARB_shader_stencil_export

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Module: Mesa
Branch: master
Commit: 160a0f255194953b9c6cd3d305a4432645c0b60b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=160a0f255194953b9c6cd3d305a4432645c0b60b

Author: Danylo Piliaiev <dpiliaiev at igalia.com>
Date:   Thu Nov 26 19:57:26 2020 +0200

freedreno/a6xx: add support for ARB_shader_stencil_export

Signed-off-by: Danylo Piliaiev <dpiliaiev at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7810>

---

 src/gallium/drivers/freedreno/a6xx/fd6_emit.c    | 5 ++++-
 src/gallium/drivers/freedreno/a6xx/fd6_program.c | 6 ++++--
 src/gallium/drivers/freedreno/freedreno_screen.c | 2 ++
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index ca21d292da2..f04c84f2038 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -589,7 +589,8 @@ compute_ztest_mode(struct fd6_emit *emit, bool lrz_valid)
 	if (fs->shader->nir->info.fs.early_fragment_tests)
 		return A6XX_EARLY_Z;
 
-	if (fs->no_earlyz || fs->writes_pos || !zsa->base.depth.enabled) {
+	if (fs->no_earlyz || fs->writes_pos || !zsa->base.depth.enabled ||
+			fs->writes_stencilref) {
 		return A6XX_LATE_Z;
 	} else if ((fs->has_kill || zsa->alpha_test) &&
 			(zsa->base.depth.writemask || !pfb->zsbuf)) {
@@ -974,6 +975,8 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
 		OUT_RING(ring, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
 				COND(fs->writes_smask && pfb->samples > 1,
 						A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
+				COND(fs->writes_stencilref,
+						A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF) |
 				COND(blend->use_dual_src_blend,
 						A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
 		OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 512a016a98d..f372123224a 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -351,6 +351,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
 	uint32_t clip0_regid, clip1_regid;
 	uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
 	uint32_t smask_in_regid, smask_regid;
+	uint32_t stencilref_regid;
 	uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
 	uint32_t hs_invocation_regid;
 	uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_patch_regid, ds_patch_regid;
@@ -440,6 +441,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
 	zwcoord_regid   = next_regid(coord_regid, 2);
 	posz_regid      = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
 	smask_regid     = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
+	stencilref_regid = ir3_find_output_regid(fs, FRAG_RESULT_STENCIL);
 	for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
 		ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
 
@@ -489,9 +491,9 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
 	OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
 	OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
 			 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
+			 A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(stencilref_regid) |
 			 COND(fs_has_dual_src_color,
-					A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
-			 0xfc000000);
+					A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
 
 	enum a3xx_threadsize vssz;
 	if (ds || hs) {
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index b437f0fb853..2389e17fd0f 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -466,6 +466,8 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 		return screen->has_syncobj;
 	case PIPE_CAP_CULL_DISTANCE:
 		return is_a6xx(screen);
+	case PIPE_CAP_SHADER_STENCIL_EXPORT:
+		return is_a6xx(screen);
 	default:
 		return u_pipe_screen_get_param_defaults(pscreen, param);
 	}