Mesa (master): radv: implement vulkan_resource_reindex

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 00d52492bfd68a35843ed065d149f5dff8ba8528
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=00d52492bfd68a35843ed065d149f5dff8ba8528

Author: Rhys Perry <pendingchaos02 at gmail.com>
Date:   Wed Mar 10 16:47:15 2021 +0000

radv: implement vulkan_resource_reindex

Fixes dEQP-VK.spirv_assembly.instruction.compute.variable_pointers.dynamic_offset.select_descriptor_array

Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9523>

---

 src/amd/llvm/ac_nir_to_llvm.c | 14 --------------
 src/amd/vulkan/radv_shader.c  | 28 ++++++++++++++++++++++++++--
 2 files changed, 26 insertions(+), 16 deletions(-)

diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index 359500cd2bb..1b181c1ce47 100644
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -1541,17 +1541,6 @@ static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx, const nir_te
    return ac_build_image_opcode(&ctx->ac, args);
 }
 
-static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
-                                                  nir_intrinsic_instr *instr)
-{
-   LLVMValueRef ptr = get_src(ctx, instr->src[0]);
-   LLVMValueRef index = get_src(ctx, instr->src[1]);
-
-   LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
-   LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
-   return result;
-}
-
 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx, nir_intrinsic_instr *instr)
 {
    LLVMValueRef ptr, addr;
@@ -3548,9 +3537,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
       result = ctx->abi->load_resource(ctx->abi, index, desc_set, binding);
       break;
    }
-   case nir_intrinsic_vulkan_resource_reindex:
-      result = visit_vulkan_resource_reindex(ctx, instr);
-      break;
    case nir_intrinsic_store_ssbo:
       visit_store_ssbo(ctx, instr);
       break;
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index cf40d00c194..6dec0958bc8 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -266,7 +266,8 @@ mark_geom_invariant(nir_shader *nir)
 }
 
 static bool
-lower_intrinsics(nir_shader *nir, const struct radv_pipeline_key *key)
+lower_intrinsics(nir_shader *nir, const struct radv_pipeline_key *key,
+                 const struct radv_pipeline_layout *layout)
 {
    nir_function_impl *entry = nir_shader_get_entrypoint(nir);
    bool progress = false;
@@ -285,6 +286,29 @@ lower_intrinsics(nir_shader *nir, const struct radv_pipeline_key *key)
          nir_ssa_def *def = NULL;
          if (intrin->intrinsic == nir_intrinsic_load_vulkan_descriptor) {
             def = nir_vec2(&b, nir_channel(&b, intrin->src[0].ssa, 0), nir_imm_int(&b, 0));
+         } else if (intrin->intrinsic == nir_intrinsic_vulkan_resource_index) {
+            unsigned desc_set = nir_intrinsic_desc_set(intrin);
+            unsigned binding = nir_intrinsic_binding(intrin);
+            struct radv_descriptor_set_layout *desc_layout = layout->set[desc_set].layout;
+
+            nir_ssa_def *new_res = nir_vulkan_resource_index(
+               &b, 2, 32, intrin->src[0].ssa, .desc_set = desc_set, .binding = binding,
+               .desc_type = nir_intrinsic_desc_type(intrin));
+            nir_ssa_def *ptr = nir_channel(&b, new_res, 0);
+
+            nir_ssa_def *stride;
+            if (desc_layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
+                desc_layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
+               stride = nir_imm_int(&b, 16);
+            } else {
+               stride = nir_imm_int(&b, desc_layout->binding[binding].size);
+            }
+            def = nir_vec2(&b, ptr, stride);
+         } else if (intrin->intrinsic == nir_intrinsic_vulkan_resource_reindex) {
+            nir_ssa_def *ptr = nir_channel(&b, intrin->src[0].ssa, 0);
+            nir_ssa_def *stride = nir_channel(&b, intrin->src[0].ssa, 1);
+            ptr = nir_iadd(&b, ptr, nir_imul(&b, intrin->src[1].ssa, stride));
+            def = nir_vec2(&b, ptr, stride);
          } else if (intrin->intrinsic == nir_intrinsic_is_sparse_texels_resident) {
             def = nir_ieq_imm(&b, intrin->src[0].ssa, 0);
          } else if (intrin->intrinsic == nir_intrinsic_sparse_residency_code_and) {
@@ -614,7 +638,7 @@ radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module *
    NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_ubo | nir_var_mem_ssbo,
               nir_address_format_32bit_index_offset);
 
-   NIR_PASS_V(nir, lower_intrinsics, key);
+   NIR_PASS_V(nir, lower_intrinsics, key, layout);
 
    /* Lower deref operations for compute shared memory. */
    if (nir->info.stage == MESA_SHADER_COMPUTE) {