Mesa (master): radv,aco: use nir_address_format_vec2_index_32bit_offset
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gitlab-mirror at kemper.freedesktop.org
Tue Apr 27 16:18:34 UTC 2021
Module: Mesa
Branch: master
Commit: ee9b744cb5d1466960e78b1de44ad345590e348c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee9b744cb5d1466960e78b1de44ad345590e348c
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Wed Mar 10 15:47:40 2021 +0000
radv,aco: use nir_address_format_vec2_index_32bit_offset
The vec2 index helps the compiler make use of SMEM's SOFFSET field when
loading descriptors.
fossil-db (GFX10.3):
Totals from 126326 (86.37% of 146267) affected shaders:
VGPRs: 4898704 -> 4899088 (+0.01%); split: -0.02%, +0.03%
SpillSGPRs: 13490 -> 14404 (+6.78%); split: -1.10%, +7.87%
CodeSize: 306442996 -> 302277700 (-1.36%); split: -1.36%, +0.01%
MaxWaves: 3277108 -> 3276624 (-0.01%); split: +0.01%, -0.02%
Instrs: 58301101 -> 57469370 (-1.43%); split: -1.43%, +0.01%
VClause: 1208270 -> 1199264 (-0.75%); split: -1.02%, +0.28%
SClause: 2517691 -> 2432744 (-3.37%); split: -3.75%, +0.38%
Copies: 3518643 -> 3161097 (-10.16%); split: -10.45%, +0.29%
Branches: 1228383 -> 1228254 (-0.01%); split: -0.12%, +0.11%
PreSGPRs: 3973880 -> 4031099 (+1.44%); split: -0.19%, +1.63%
PreVGPRs: 3831599 -> 3831707 (+0.00%)
Cycles: 1785250712 -> 1778222316 (-0.39%); split: -0.42%, +0.03%
VMEM: 52873776 -> 50663317 (-4.18%); split: +0.18%, -4.36%
SMEM: 8534270 -> 8361666 (-2.02%); split: +1.79%, -3.82%
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9523>
---
src/amd/compiler/aco_instruction_selection.cpp | 100 ++++++++++++-------------
src/amd/compiler/tests/test_isel.cpp | 2 +-
src/amd/llvm/ac_nir_to_llvm.c | 13 +++-
src/amd/vulkan/radv_meta.c | 4 +-
src/amd/vulkan/radv_nir_to_llvm.c | 19 +++--
src/amd/vulkan/radv_pipeline.c | 11 ++-
src/amd/vulkan/radv_shader.c | 25 ++++---
7 files changed, 98 insertions(+), 76 deletions(-)
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 1c790522070..e57f60b3ef9 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -4998,46 +4998,29 @@ void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
stride = layout->binding[binding].size;
}
- nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
- unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
- if (stride != 1) {
- if (nir_const_index) {
- const_index = const_index * stride;
- } else if (index.type() == RegType::vgpr) {
+ if (nir_src_is_const(instr->src[0])) {
+ index = bld.copy(bld.def(s1), Operand((uint32_t)(offset + nir_src_as_uint(instr->src[0]) * stride)));
+ } else if (index.type() == RegType::vgpr) {
+ if (stride != 1) {
bool index24bit = layout->binding[binding].array_size <= 0x1000000;
index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
- } else {
- index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
}
- }
- if (offset) {
- if (nir_const_index) {
- const_index = const_index + offset;
- } else if (index.type() == RegType::vgpr) {
+ if (offset)
index = bld.vadd32(bld.def(v1), Operand(offset), index);
- } else {
- index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
- }
- }
-
- if (nir_const_index && const_index == 0) {
- index = desc_ptr;
- } else if (index.type() == RegType::vgpr) {
- index = bld.vadd32(bld.def(v1),
- nir_const_index ? Operand(const_index) : Operand(index),
- Operand(desc_ptr));
} else {
- index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
- nir_const_index ? Operand(const_index) : Operand(index),
- Operand(desc_ptr));
+ if (stride != 1)
+ index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index);
+ if (offset)
+ index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
}
Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
- elems[0] = index;
+ elems[0] = desc_ptr;
+ elems[1] = index;
ctx->allocated_vec.emplace(dst.id(), elems);
- bld.pseudo(aco_opcode::p_create_vector, Definition(dst), index,
- Operand((unsigned)ctx->options->address32_hi));
+ bld.pseudo(aco_opcode::p_create_vector, Definition(dst), desc_ptr, index,
+ Operand(0u));
}
void load_buffer(isel_context *ctx, unsigned num_components, unsigned component_size,
@@ -5061,6 +5044,25 @@ void load_buffer(isel_context *ctx, unsigned num_components, unsigned component_
emit_load(ctx, bld, info, mubuf_load_params);
}
+Temp load_buffer_rsrc(isel_context *ctx, Temp rsrc)
+{
+ Builder bld(ctx->program, ctx->block);
+ Temp set_ptr = emit_extract_vector(ctx, rsrc, 0, RegClass(rsrc.type(), 1));
+ Temp binding = bld.as_uniform(emit_extract_vector(ctx, rsrc, 1, RegClass(rsrc.type(), 1)));
+ set_ptr = convert_pointer_to_64_bit(ctx, set_ptr);
+ return bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), set_ptr, binding);
+}
+
+bool is_inline_ubo(isel_context *ctx, nir_src rsrc)
+{
+ nir_binding binding = nir_chase_binding(rsrc);
+ if (!binding.success)
+ return false;
+
+ radv_descriptor_set_layout *layout = ctx->options->layout->set[binding.desc_set].layout;
+ return layout->binding[binding.binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT;
+}
+
void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
{
Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
@@ -5068,11 +5070,11 @@ void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
Builder bld(ctx->program, ctx->block);
- nir_binding binding = nir_chase_binding(instr->src[0]);
- assert(binding.success);
- radv_descriptor_set_layout *layout = ctx->options->layout->set[binding.desc_set].layout;
+ if (is_inline_ubo(ctx, instr->src[0])) {
+ Temp set_ptr = bld.as_uniform(emit_extract_vector(ctx, rsrc, 0, RegClass(rsrc.type(), 1)));
+ Temp binding_off = bld.as_uniform(emit_extract_vector(ctx, rsrc, 1, RegClass(rsrc.type(), 1)));
+ rsrc = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), set_ptr, binding_off);
- if (layout->binding[binding.binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
@@ -5085,15 +5087,11 @@ void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
}
- Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
- Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
- Operand(0xFFFFFFFFu),
- Operand(desc_type));
- rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
- rsrc, upper_dwords);
+ rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), rsrc,
+ Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
+ Operand(0xFFFFFFFFu), Operand(desc_type));
} else {
- rsrc = convert_pointer_to_64_bit(ctx, rsrc);
- rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
+ rsrc = load_buffer_rsrc(ctx, rsrc);
}
unsigned size = instr->dest.ssa.bit_size / 8;
load_buffer(ctx, instr->num_components, size, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa),
@@ -6190,8 +6188,7 @@ void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
unsigned num_components = instr->num_components;
Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
- Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
- rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
+ Temp rsrc = load_buffer_rsrc(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
unsigned access = nir_intrinsic_access(instr);
bool glc = access & (ACCESS_VOLATILE | ACCESS_COHERENT);
@@ -6217,8 +6214,7 @@ void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
unsigned writemask = widen_mask(nir_intrinsic_write_mask(instr), elem_size_bytes);
Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
- Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
- rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
+ Temp rsrc = load_buffer_rsrc(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
memory_sync_info sync = get_memory_sync_info(instr, storage_buffer, 0);
bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
@@ -6269,8 +6265,7 @@ void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
get_ssa_temp(ctx, instr->src[3].ssa), data);
Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
- Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
- rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
+ Temp rsrc = load_buffer_rsrc(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
@@ -6342,17 +6337,20 @@ void visit_get_ssbo_size(isel_context *ctx, nir_intrinsic_instr *instr) {
Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
bool non_uniform = dst.type() == RegType::vgpr;
- Temp index = convert_pointer_to_64_bit(ctx, rsrc, non_uniform);
Builder bld(ctx->program, ctx->block);
if (non_uniform) {
+ Temp set_ptr = emit_extract_vector(ctx, rsrc, 0, RegClass(rsrc.type(), 1));
+ Temp binding = emit_extract_vector(ctx, rsrc, 1, RegClass(rsrc.type(), 1));
+ Temp index = bld.vadd32(bld.def(v1), set_ptr, binding);
+ index = convert_pointer_to_64_bit(ctx, index, non_uniform);
+
LoadEmitInfo info = {Operand(index), dst, 1, 4};
info.align_mul = 4;
info.const_offset = 8;
emit_load(ctx, bld, info, global_load_params);
} else {
- Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
- emit_extract_vector(ctx, desc, 2, dst);
+ emit_extract_vector(ctx, load_buffer_rsrc(ctx, rsrc), 2, dst);
}
}
diff --git a/src/amd/compiler/tests/test_isel.cpp b/src/amd/compiler/tests/test_isel.cpp
index 9c11a07e7f9..6434553eadf 100644
--- a/src/amd/compiler/tests/test_isel.cpp
+++ b/src/amd/compiler/tests/test_isel.cpp
@@ -145,7 +145,7 @@ BEGIN_TEST(isel.sparse.clause)
QO_EXTENSION GL_ARB_sparse_texture2 : require
layout(local_size_x=1) in;
layout(binding=0) uniform sampler2D tex;
- layout(binding=0) buffer Buf {
+ layout(binding=1) buffer Buf {
vec4 res[4];
uint code[4];
};
diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index 1b181c1ce47..fd58c722714 100644
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -492,15 +492,20 @@ static LLVMValueRef enter_waterfall(struct ac_nir_context *ctx, struct waterfall
ac_build_bgnloop(&ctx->ac, 6000);
- LLVMValueRef scalar_value = ac_build_readlane(&ctx->ac, value, NULL);
+ LLVMValueRef active = LLVMConstInt(ctx->ac.i1, 1, false);
+ LLVMValueRef scalar_value[NIR_MAX_VEC_COMPONENTS];
- LLVMValueRef active =
- LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, value, scalar_value, "uniform_active");
+ for (unsigned i = 0; i < ac_get_llvm_num_components(value); i++) {
+ LLVMValueRef comp = ac_llvm_extract_elem(&ctx->ac, value, i);
+ scalar_value[i] = ac_build_readlane(&ctx->ac, comp, NULL);
+ active = LLVMBuildAnd(ctx->ac.builder, active,
+ LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, comp, scalar_value[i], ""), "");
+ }
wctx->phi_bb[0] = LLVMGetInsertBlock(ctx->ac.builder);
ac_build_ifcc(&ctx->ac, active, 6001);
- return scalar_value;
+ return ac_build_gather_values(&ctx->ac, scalar_value, ac_get_llvm_num_components(value));
}
static LLVMValueRef exit_waterfall(struct ac_nir_context *ctx, struct waterfall_context *wctx,
diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index db456e146a7..6206aa055e7 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -653,7 +653,7 @@ radv_meta_build_resolve_shader_core(nir_builder *b, bool is_integer, int samples
nir_ssa_def *
radv_meta_load_descriptor(nir_builder *b, unsigned desc_set, unsigned binding)
{
- nir_ssa_def *rsrc = nir_vulkan_resource_index(b, 2, 32, nir_imm_int(b, 0), .desc_set = desc_set,
+ nir_ssa_def *rsrc = nir_vulkan_resource_index(b, 3, 32, nir_imm_int(b, 0), .desc_set = desc_set,
.binding = binding);
- return nir_channel(b, rsrc, 0);
+ return nir_channels(b, rsrc, 0x3);
}
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 2e140b4a724..e72e091f909 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -223,11 +223,10 @@ radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index, unsigned desc_
offset = ac_build_imad(&ctx->ac, index, stride, offset);
}
- desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
desc_ptr = LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.i32, "");
- LLVMValueRef res[] = {desc_ptr, ctx->ac.i32_0};
- return ac_build_gather_values(&ctx->ac, res, 2);
+ LLVMValueRef res[] = {desc_ptr, offset, ctx->ac.i32_0};
+ return ac_build_gather_values(&ctx->ac, res, 3);
}
static uint32_t
@@ -416,8 +415,12 @@ radv_load_base_vertex(struct ac_shader_abi *abi, bool non_indexed_is_zero)
}
static LLVMValueRef
-convert_pointer_to_64_bit(struct radv_shader_context *ctx, LLVMValueRef ptr, bool non_uniform)
+get_desc_ptr(struct radv_shader_context *ctx, LLVMValueRef ptr, bool non_uniform)
{
+ LLVMValueRef set_ptr = ac_llvm_extract_elem(&ctx->ac, ptr, 0);
+ LLVMValueRef offset = ac_llvm_extract_elem(&ctx->ac, ptr, 1);
+ ptr = LLVMBuildNUWAdd(ctx->ac.builder, set_ptr, offset, "");
+
unsigned addr_space = AC_ADDR_SPACE_CONST_32BIT;
if (non_uniform) {
/* 32-bit seems to always use SMEM. addrspacecast from 32-bit -> 64-bit is broken. */
@@ -436,7 +439,7 @@ radv_load_ssbo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr, bool write, b
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef result;
- buffer_ptr = convert_pointer_to_64_bit(ctx, buffer_ptr, non_uniform);
+ buffer_ptr = get_desc_ptr(ctx, buffer_ptr, non_uniform);
if (!non_uniform)
LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
@@ -458,6 +461,10 @@ radv_load_ubo(struct ac_shader_abi *abi, unsigned desc_set, unsigned binding, bo
struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
+ LLVMValueRef set_ptr = ac_llvm_extract_elem(&ctx->ac, buffer_ptr, 0);
+ LLVMValueRef offset = ac_llvm_extract_elem(&ctx->ac, buffer_ptr, 1);
+ buffer_ptr = LLVMBuildNUWAdd(ctx->ac.builder, set_ptr, offset, "");
+
uint32_t desc_type =
S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
@@ -482,7 +489,7 @@ radv_load_ubo(struct ac_shader_abi *abi, unsigned desc_set, unsigned binding, bo
}
}
- buffer_ptr = convert_pointer_to_64_bit(ctx, buffer_ptr, false);
+ buffer_ptr = get_desc_ptr(ctx, buffer_ptr, false);
LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 81983334d2a..c4ee3e9e5b4 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3174,6 +3174,14 @@ opt_vectorize_callback(const nir_instr *instr, void *_)
}
}
+static nir_component_mask_t
+non_uniform_access_callback(const nir_src *src, void *_)
+{
+ if (src->ssa->num_components == 1)
+ return 0x1;
+ return nir_chase_binding(*src).success ? 0x2 : 0x3;
+}
+
VkResult
radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device,
struct radv_pipeline_cache *cache, const struct radv_pipeline_key *pipeline_key,
@@ -3305,7 +3313,8 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device,
nir_lower_non_uniform_access_options options = {
.types = nir_lower_non_uniform_ubo_access | nir_lower_non_uniform_ssbo_access |
nir_lower_non_uniform_texture_access | nir_lower_non_uniform_image_access,
- .callback = NULL,
+ .callback = &non_uniform_access_callback,
+ .callback_data = NULL,
};
NIR_PASS_V(nir[i], nir_lower_non_uniform_access, &options);
}
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 6dec0958bc8..4a0d67408e1 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -285,16 +285,18 @@ lower_intrinsics(nir_shader *nir, const struct radv_pipeline_key *key,
nir_ssa_def *def = NULL;
if (intrin->intrinsic == nir_intrinsic_load_vulkan_descriptor) {
- def = nir_vec2(&b, nir_channel(&b, intrin->src[0].ssa, 0), nir_imm_int(&b, 0));
+ def = nir_vec3(&b, nir_channel(&b, intrin->src[0].ssa, 0),
+ nir_channel(&b, intrin->src[0].ssa, 1), nir_imm_int(&b, 0));
} else if (intrin->intrinsic == nir_intrinsic_vulkan_resource_index) {
unsigned desc_set = nir_intrinsic_desc_set(intrin);
unsigned binding = nir_intrinsic_binding(intrin);
struct radv_descriptor_set_layout *desc_layout = layout->set[desc_set].layout;
nir_ssa_def *new_res = nir_vulkan_resource_index(
- &b, 2, 32, intrin->src[0].ssa, .desc_set = desc_set, .binding = binding,
+ &b, 3, 32, intrin->src[0].ssa, .desc_set = desc_set, .binding = binding,
.desc_type = nir_intrinsic_desc_type(intrin));
- nir_ssa_def *ptr = nir_channel(&b, new_res, 0);
+ nir_ssa_def *set_ptr = nir_channel(&b, new_res, 0);
+ nir_ssa_def *binding_ptr = nir_channel(&b, new_res, 1);
nir_ssa_def *stride;
if (desc_layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
@@ -303,12 +305,13 @@ lower_intrinsics(nir_shader *nir, const struct radv_pipeline_key *key,
} else {
stride = nir_imm_int(&b, desc_layout->binding[binding].size);
}
- def = nir_vec2(&b, ptr, stride);
+ def = nir_vec3(&b, set_ptr, binding_ptr, stride);
} else if (intrin->intrinsic == nir_intrinsic_vulkan_resource_reindex) {
- nir_ssa_def *ptr = nir_channel(&b, intrin->src[0].ssa, 0);
- nir_ssa_def *stride = nir_channel(&b, intrin->src[0].ssa, 1);
- ptr = nir_iadd(&b, ptr, nir_imul(&b, intrin->src[1].ssa, stride));
- def = nir_vec2(&b, ptr, stride);
+ nir_ssa_def *set_ptr = nir_channel(&b, intrin->src[0].ssa, 0);
+ nir_ssa_def *binding_ptr = nir_channel(&b, intrin->src[0].ssa, 1);
+ nir_ssa_def *stride = nir_channel(&b, intrin->src[0].ssa, 2);
+ binding_ptr = nir_iadd(&b, binding_ptr, nir_imul(&b, intrin->src[1].ssa, stride));
+ def = nir_vec3(&b, set_ptr, binding_ptr, stride);
} else if (intrin->intrinsic == nir_intrinsic_is_sparse_texels_resident) {
def = nir_ieq_imm(&b, intrin->src[0].ssa, 0);
} else if (intrin->intrinsic == nir_intrinsic_sparse_residency_code_and) {
@@ -457,8 +460,8 @@ radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module *
.fragment_shading_rate = device->physical_device->rad_info.chip_class >= GFX10_3,
.workgroup_memory_explicit_layout = true,
},
- .ubo_addr_format = nir_address_format_32bit_index_offset,
- .ssbo_addr_format = nir_address_format_32bit_index_offset,
+ .ubo_addr_format = nir_address_format_vec2_index_32bit_offset,
+ .ssbo_addr_format = nir_address_format_vec2_index_32bit_offset,
.phys_ssbo_addr_format = nir_address_format_64bit_global,
.push_const_addr_format = nir_address_format_logical,
.shared_addr_format = nir_address_format_32bit_offset,
@@ -636,7 +639,7 @@ radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module *
NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const, nir_address_format_32bit_offset);
NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_ubo | nir_var_mem_ssbo,
- nir_address_format_32bit_index_offset);
+ nir_address_format_vec2_index_32bit_offset);
NIR_PASS_V(nir, lower_intrinsics, key, layout);
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