Mesa (main): pan/va: Add more assembler tests

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Module: Mesa
Branch: main
Commit: 7d157ae50ed04f8f7d02456f1eac578500fc8656
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d157ae50ed04f8f7d02456f1eac578500fc8656

Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Mon Aug  2 12:31:40 2021 -0400

pan/va: Add more assembler tests

For new patterns

Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14065>

---

 src/panfrost/bifrost/valhall/test/assembler-cases.txt | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/panfrost/bifrost/valhall/test/assembler-cases.txt b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
index b3fd7005ed1..7d2e48df398 100644
--- a/src/panfrost/bifrost/valhall/test/assembler-cases.txt
+++ b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
@@ -58,6 +58,7 @@ f0 00 3c 33 04 40 7f 78    BLEND.slot0.v4.f16.return @r0:r1, @r60, blend_descrip
 41 88 c0 00 04 c1 b2 00    FMA.f32 r1, `r1, u8, 0x0.neg
 40 88 c0 00 04 c0 b2 10    FMA.f32.wait1 r0, `r0, u8, 0x0.neg
 44 00 00 32 06 40 61 78    STORE.i96.vary.slot0.return @r0:r1:r2, `r4, offset:0
+44 00 00 39 08 48 61 78    STORE.i128.pos.slot0.return @r8:r9:r10:r11, `r4, offset:0
 00 00 00 c0 01 c0 45 48    BARRIER.slot7.barrier 
 80 00 00 00 82 82 60 00    LOAD.i8.unsigned.slot0 @r2, u0, offset:0
 80 00 00 08 82 82 60 00    LOAD.i16.unsigned.slot0 @r2, u0, offset:0
@@ -119,3 +120,15 @@ c0 01 00 00 00 c4 10 51    IADD_IMM.i32.reconverge r4, 0x0, #0x1
 83 84 00 28 f4 82 6a 00    LD_BUFFER.i64.unsigned.slot0 @r2:r3, u3, u4
 41 82 00 30 e6 82 6a 00    LD_BUFFER.i96.unsigned.slot0 @r2:r3:r4, `r1, u2
 40 83 00 30 e6 86 6a 08    LD_BUFFER.i96.unsigned.slot0.wait0 @r6:r7:r8, `r0, u3
+40 00 00 00 c0 c0 9c 40    FRCP.f32.wait0126 r0, `r0.neg.abs
+40 44 80 00 00 c0 b8 00    MUX.i32.neg r0, `r0, `r4, u0
+40 44 80 00 01 c0 b8 00    MUX.i32 r0, `r0, `r4, u0
+40 44 80 00 02 c0 b8 00    MUX.i32.fp_zero r0, `r0, `r4, u0
+40 44 80 00 03 c0 b8 00    MUX.i32.bit r0, `r0, `r4, u0
+00 00 00 01 00 c1 99 68    FREXPM.f32.sqrt.td r1, r0
+01 00 02 00 00 c2 9c 00    FRSQ.f32 r2, r1
+40 00 02 01 00 c0 99 00    FREXPE.f32.sqrt r0, `r0
+41 42 c0 40 04 c0 62 41    FMA_RSCALE_LEFT.f32.wait0126 r0, `r1, `r2, 0x0.neg, `r0
+42 43 84 85 00 c1 50 01    CSEL.u32.eq r1, `r2, `r3, u4, u5
+42 43 84 85 04 c1 50 01    CSEL.u32.lt r1, `r2, `r3, u4, u5
+42 43 84 85 04 c1 58 01    CSEL.s32.lt r1, `r2, `r3, u4, u5