Mesa (main): pan/va: Add sample/update modes to LD_VAR

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Module: Mesa
Branch: main
Commit: a5084127eb7c528f09717708fe42776944e247c2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5084127eb7c528f09717708fe42776944e247c2

Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Sat Dec  4 20:28:10 2021 -0500

pan/va: Add sample/update modes to LD_VAR

..and test the new instructions. As usual, the semantics are the same as
bifrost, but the encoding is simpler.

Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14065>

---

 src/panfrost/bifrost/valhall/ISA.xml               | 28 ++++++++++++++++++++++
 .../bifrost/valhall/test/assembler-cases.txt       |  4 ++++
 src/panfrost/bifrost/valhall/valhall.py            |  2 ++
 3 files changed, 34 insertions(+)

diff --git a/src/panfrost/bifrost/valhall/ISA.xml b/src/panfrost/bifrost/valhall/ISA.xml
index fd811496e6d..5db8ff56a02 100644
--- a/src/panfrost/bifrost/valhall/ISA.xml
+++ b/src/panfrost/bifrost/valhall/ISA.xml
@@ -590,6 +590,30 @@
     <value desc="Bitwise">bit</value>
   </enum>
 
+  <enum name="Sample mode">
+    <desc>
+      Varying interpolation mode, for choosing the correct sample to
+      interpolate at, allowing the `sample` and `centroid` qualifiers to be
+      implemented, as well as the `interpolateAt*` functions.
+    </desc>
+    <value desc="Center">center</value>
+    <value desc="Centroid">centroid</value>
+    <value desc="Sample">sample</value>
+    <value desc="Explicit">explicit</value>
+  </enum>
+
+  <enum name="Update mode">
+    <desc>
+      The Valhall GPU maintains hidden state when interpolating varyings, to
+      allow reusing sample location calculations. The update mode of a varying
+      load controls this hidden state.
+    </desc>
+    <value desc="Store interpolation position">store</value>
+    <value desc="Retrieve interpolation position">retrieve</value>
+    <reserved/>
+    <value desc="Clobber saved position">clobber</value>
+  </enum>
+
   <ins name="NOP" title="No operation" dests="0" opcode="0x00" unit="CVT">
     <desc>
       Do nothing. Useful at the start of a block for waiting on slots required
@@ -689,6 +713,8 @@
     <sr_count/>
     <vecsize/>
     <regfmt/>
+    <sample/>
+    <update/>
     <slot/>
     <src/>
     <imm name="index" start="12" size="4"/> <!-- 0 for pointx, 1 for pointy, 2 for fragw, 3 for fragz -->
@@ -702,6 +728,8 @@
     <vecsize/>
     <sr_count/>
     <regfmt/>
+    <sample/>
+    <update/>
     <slot/>
     <src/>
     <src/>
diff --git a/src/panfrost/bifrost/valhall/test/assembler-cases.txt b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
index 7d2e48df398..e80abc80694 100644
--- a/src/panfrost/bifrost/valhall/test/assembler-cases.txt
+++ b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
@@ -132,3 +132,7 @@ c0 01 00 00 00 c4 10 51    IADD_IMM.i32.reconverge r4, 0x0, #0x1
 42 43 84 85 00 c1 50 01    CSEL.u32.eq r1, `r2, `r3, u4, u5
 42 43 84 85 04 c1 50 01    CSEL.u32.lt r1, `r2, `r3, u4, u5
 42 43 84 85 04 c1 58 01    CSEL.s32.lt r1, `r2, `r3, u4, u5
+3d 00 00 12 b4 82 56 08    LD_VAR_SPECIAL.v2.f32.sample.clobber.slot0.wait0 @r2:r3, r61, index:0x0
+3d 00 00 33 14 82 5d 08    LD_VAR_IMM_F16.v4.f16.center.retrieve.slot0.wait0 @r2:r3, r61, r0, index:0x0
+3d 00 00 33 84 80 5d 08    LD_VAR_IMM_F16.v4.f16.sample.store.slot0.wait0 @r0:r1, r61, r0, index:0x0
+3d 00 08 33 44 80 5d 08    LD_VAR_IMM_F16.v4.f16.centroid.store.slot0.wait0 @r0:r1, r61, r0, index:0x8
diff --git a/src/panfrost/bifrost/valhall/valhall.py b/src/panfrost/bifrost/valhall/valhall.py
index 7ce5417c494..5056aec8f61 100644
--- a/src/panfrost/bifrost/valhall/valhall.py
+++ b/src/panfrost/bifrost/valhall/valhall.py
@@ -350,6 +350,8 @@ MODIFIERS = {
     "sr_count": Modifier("staging_register_count", 33, 3, implied = True),
 
     "subgroup": Modifier("subgroup_size", 36, 2),
+    "update": Modifier("update_mode", 36, 2),
+    "sample": Modifier("sample_mode", 38, 2),
 }
 
 # Parse the ISA