Mesa (main): pan/va: Add table parameter to LD_ATTR_IMM

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Module: Mesa
Branch: main
Commit: 46b758cbccff9a38339f6e5048665c31871e94f4
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=46b758cbccff9a38339f6e5048665c31871e94f4

Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Sat Dec  4 20:28:45 2021 -0500

pan/va: Add table parameter to LD_ATTR_IMM

..and test the instruction.

Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14065>

---

 src/panfrost/bifrost/valhall/ISA.xml                  | 6 ++++++
 src/panfrost/bifrost/valhall/test/assembler-cases.txt | 1 +
 2 files changed, 7 insertions(+)

diff --git a/src/panfrost/bifrost/valhall/ISA.xml b/src/panfrost/bifrost/valhall/ISA.xml
index 5db8ff56a02..8c9c55afac4 100644
--- a/src/panfrost/bifrost/valhall/ISA.xml
+++ b/src/panfrost/bifrost/valhall/ISA.xml
@@ -737,6 +737,11 @@
   </group>
 
   <ins name="LD_ATTR_IMM" title="Load immediate attribute" opcode="0x66" unit="LS">
+    <desc>
+      Load `vecsize` components from the attribute descriptor at entry `index`
+      of resource table `table` at index (vertex ID, instance ID), converting
+      to the specified register format.
+    </desc>
     <sr_count/>
     <vecsize/>
     <regfmt/>
@@ -745,6 +750,7 @@
     <src>Vertex ID</src>
     <src>Instance ID</src>
     <imm name="index" start="20" size="4"/>
+    <imm name="table" start="16" size="4"/>
   </ins>
 
   <ins name="LEA_IMAGE_IMM" title="Load effective address of image texel" opcode="0x67" unit="LS">
diff --git a/src/panfrost/bifrost/valhall/test/assembler-cases.txt b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
index e80abc80694..0240de3c32b 100644
--- a/src/panfrost/bifrost/valhall/test/assembler-cases.txt
+++ b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
@@ -136,3 +136,4 @@ c0 01 00 00 00 c4 10 51    IADD_IMM.i32.reconverge r4, 0x0, #0x1
 3d 00 00 33 14 82 5d 08    LD_VAR_IMM_F16.v4.f16.center.retrieve.slot0.wait0 @r2:r3, r61, r0, index:0x0
 3d 00 00 33 84 80 5d 08    LD_VAR_IMM_F16.v4.f16.sample.store.slot0.wait0 @r0:r1, r61, r0, index:0x0
 3d 00 08 33 44 80 5d 08    LD_VAR_IMM_F16.v4.f16.centroid.store.slot0.wait0 @r0:r1, r61, r0, index:0x8
+7c 7d 11 33 04 80 66 00    LD_ATTR_IMM.v4.f16.slot0 @r0:r1, `r60, `r61, index:0x1, table:0x1