Mesa (master): gv100/ir: Make emitATOM consistent with emitRED

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Module: Mesa
Branch: master
Commit: b02e3053ea478e5d1f4b96d107e1a5d12233e055
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b02e3053ea478e5d1f4b96d107e1a5d12233e055

Author: Alistair Popple <apopple at nvidia.com>
Date:   Mon Dec  7 12:42:52 2020 +1100

gv100/ir: Make emitATOM consistent with emitRED

GV100 code generation uses ATOM instructions for compare-and-swap and
RED instructions for other atomic operations. Make the scope consistent
for both types of operations.

Signed-off-by: Alistair Popple <apopple at nvidia.com>
Reviewed-by: Ben Skeggs <bskeggs at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7955>

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp
index 0758ef09331..1d60bc766ab 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp
@@ -862,7 +862,8 @@ CodeEmitterGV100::emitATOM()
    }
 
    emitPRED (81);
-   emitField(79, 2, 1);
+   emitField(79, 2, 2); // .INVALID0/./.STRONG/.INVALID3
+   emitField(77, 2, 2); // .CTA/.SM/.GPU/.SYS
    emitField(72, 1, insn->src(0).getIndirect(0)->getSize() == 8);
    emitGPR  (32, insn->src(1));
    emitADDR (24, 40, 24, 0, insn->src(0));