Mesa (master): radv: re-initialize HTILE properly after depth/stencil compute resolves

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Module: Mesa
Branch: master
Commit: 1645d9ebabecb7946f3710c6632bcfc210fcd522
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1645d9ebabecb7946f3710c6632bcfc210fcd522

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Fri Jan  8 14:35:36 2021 +0100

radv: re-initialize HTILE properly after depth/stencil compute resolves

This was added to workaround some CTS failures which no longer happen.
Note that radv_clear_htile() will only clear the depth or stencil
bytes of the HTILE buffer based on the aspect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8389>

---

 src/amd/vulkan/radv_meta_resolve_cs.c | 35 ++++++++++++-----------------------
 1 file changed, 12 insertions(+), 23 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c
index 41bfa4ff18b..934aab4aed1 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -982,29 +982,18 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
 	                                RADV_CMD_FLAG_INV_VCACHE;
 
 	if (radv_image_has_htile(dst_image)) {
-		if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
-			VkImageSubresourceRange range = {0};
-			range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT;
-			range.baseMipLevel = dst_iview->base_mip;
-			range.levelCount = 1;
-			range.baseArrayLayer = dst_iview->base_layer;
-			range.layerCount = layer_count;
-
-			uint32_t clear_value = 0xfffc000f;
-
-			if (vk_format_is_stencil(dst_image->vk_format) &&
-			    subpass->stencil_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
-				/* Only clear the stencil part of the HTILE
-				 * buffer if it's resolved, otherwise this
-				 * might break if the stencil has been cleared.
-				 */
-				clear_value = 0xfffff3ff;
-			}
-
-			cmd_buffer->state.flush_bits |=
-				radv_clear_htile(cmd_buffer, dst_image, &range,
-						 clear_value);
-		}
+		VkImageSubresourceRange range = {0};
+		range.aspectMask = aspects;
+		range.baseMipLevel = dst_iview->base_mip;
+		range.levelCount = 1;
+		range.baseArrayLayer = dst_iview->base_layer;
+		range.layerCount = layer_count;
+
+		uint32_t htile_value =
+			radv_get_htile_initial_value(cmd_buffer->device, dst_image);
+
+		cmd_buffer->state.flush_bits |=
+			radv_clear_htile(cmd_buffer, dst_image, &range, htile_value);
 	}
 
 	radv_meta_restore(&saved_state, cmd_buffer);