Mesa (master): ac/surf: Prepare for 64-bit flags.
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Mon Jan 11 12:20:21 UTC 2021
Module: Mesa
Branch: master
Commit: dea1c06c9ba26ea523b5aef9d923349d0159ab06
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dea1c06c9ba26ea523b5aef9d923349d0159ab06
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Sat Nov 28 02:46:29 2020 +0100
ac/surf: Prepare for 64-bit flags.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
---
src/amd/common/ac_surface.c | 4 ++--
src/amd/common/ac_surface.h | 22 +++++++++++-----------
src/amd/vulkan/radv_image.c | 6 +++---
src/gallium/drivers/r600/r600_texture.c | 2 +-
src/gallium/drivers/radeonsi/si_texture.c | 3 ++-
5 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 855bf043698..91fde63a1a7 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -2904,7 +2904,7 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
fprintf(out,
" Surf: size=%" PRIu64 ", slice_size=%" PRIu64 ", "
"alignment=%u, swmode=%u, epitch=%u, pitch=%u, blk_w=%u, "
- "blk_h=%u, bpe=%u, flags=0x%x\n",
+ "blk_h=%u, bpe=%u, flags=0x%"PRIx64"\n",
surf->surf_size, surf->u.gfx9.surf_slice_size,
surf->surf_alignment, surf->u.gfx9.surf.swizzle_mode,
surf->u.gfx9.surf.epitch, surf->u.gfx9.surf_pitch,
@@ -2947,7 +2947,7 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
} else {
fprintf(out,
" Surf: size=%" PRIu64 ", alignment=%u, blk_w=%u, blk_h=%u, "
- "bpe=%u, flags=0x%x\n",
+ "bpe=%u, flags=0x%"PRIx64"\n",
surf->surf_size, surf->surf_alignment, surf->blk_w,
surf->blk_h, surf->bpe, surf->flags);
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 00912d25a0f..017c7a624fd 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -70,18 +70,18 @@ enum radeon_micro_mode
#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
#define RADEON_SURF_FMASK (1 << 21)
-#define RADEON_SURF_DISABLE_DCC (1 << 22)
-#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
-#define RADEON_SURF_IMPORTED (1 << 24)
-#define RADEON_SURF_CONTIGUOUS_DCC_LAYERS (1 << 25)
-#define RADEON_SURF_SHAREABLE (1 << 26)
-#define RADEON_SURF_NO_RENDER_TARGET (1 << 27)
+#define RADEON_SURF_DISABLE_DCC (1ull << 22)
+#define RADEON_SURF_TC_COMPATIBLE_HTILE (1ull << 23)
+#define RADEON_SURF_IMPORTED (1ull << 24)
+#define RADEON_SURF_CONTIGUOUS_DCC_LAYERS (1ull << 25)
+#define RADEON_SURF_SHAREABLE (1ull << 26)
+#define RADEON_SURF_NO_RENDER_TARGET (1ull << 27)
/* Force a swizzle mode (gfx9+) or tile mode (gfx6-8).
* If this is not set, optimize for space. */
-#define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28)
-#define RADEON_SURF_NO_FMASK (1 << 29)
-#define RADEON_SURF_NO_HTILE (1 << 30)
-#define RADEON_SURF_FORCE_MICRO_TILE_MODE (1u << 31)
+#define RADEON_SURF_FORCE_SWIZZLE_MODE (1ull << 28)
+#define RADEON_SURF_NO_FMASK (1ull << 29)
+#define RADEON_SURF_NO_HTILE (1ull << 30)
+#define RADEON_SURF_FORCE_MICRO_TILE_MODE (1ull << 31)
struct legacy_surf_level {
uint64_t offset;
@@ -206,7 +206,7 @@ struct radeon_surf {
unsigned is_displayable : 1;
/* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
unsigned micro_tile_mode : 3;
- uint32_t flags;
+ uint64_t flags;
/*
* DRM format modifier. Set to DRM_FORMAT_MOD_INVALID to have addrlib
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 80d1401583f..f8e3359bdad 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -411,14 +411,14 @@ radv_patch_image_from_extra_info(struct radv_device *device,
return VK_SUCCESS;
}
-static uint32_t
+static uint64_t
radv_get_surface_flags(struct radv_device *device,
const struct radv_image *image,
unsigned plane_id,
const VkImageCreateInfo *pCreateInfo,
VkFormat image_format)
{
- uint32_t flags;
+ uint64_t flags;
unsigned array_mode = radv_choose_tiling(device, pCreateInfo, image_format);
VkFormat format = vk_format_get_plane_format(image_format, plane_id);
const struct vk_format_description *desc = vk_format_description(format);
@@ -1298,7 +1298,7 @@ radv_image_reset_layout(struct radv_image *image)
for (unsigned i = 0; i < image->plane_count; ++i) {
VkFormat format = vk_format_get_plane_format(image->vk_format, i);
- uint32_t flags = image->planes[i].surface.flags;
+ uint64_t flags = image->planes[i].surface.flags;
uint64_t modifier = image->planes[i].surface.modifier;
memset(image->planes + i, 0, sizeof(image->planes[i]));
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 75cbbf0cf06..d2acfc81374 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -830,7 +830,7 @@ void r600_print_texture_info(struct r600_common_screen *rscreen,
/* Common parameters. */
u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
"blk_h=%u, array_size=%u, last_level=%u, "
- "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
+ "bpe=%u, nsamples=%u, flags=0x%"PRIx64", %s\n",
rtex->resource.b.b.width0, rtex->resource.b.b.height0,
rtex->resource.b.b.depth0, rtex->surface.blk_w,
rtex->surface.blk_h,
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 13d197bdb62..05d93a21aee 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -162,7 +162,8 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
const struct util_format_description *desc = util_format_description(ptex->format);
bool is_depth, is_stencil;
int r;
- unsigned bpe, flags = 0;
+ unsigned bpe;
+ uint64_t flags = 0;
is_depth = util_format_has_depth(desc);
is_stencil = util_format_has_stencil(desc);
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