Mesa (master): ac/surf: Implement PRT layout.
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Mon Jan 11 12:20:21 UTC 2021
Module: Mesa
Branch: master
Commit: cd5458f3671916f98a37d85b45ecfc913044fd11
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd5458f3671916f98a37d85b45ecfc913044fd11
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Sat Nov 28 02:51:05 2020 +0100
ac/surf: Implement PRT layout.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
---
src/amd/common/ac_surface.c | 11 +++++++++++
src/amd/common/ac_surface.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 91fde63a1a7..b9b0e573fed 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1189,6 +1189,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
+ AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0;
/* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
* requested, because TC-compatible HTILE requires 2D tiling.
@@ -1523,6 +1524,15 @@ static int gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, struct radeon_su
sin.flags.fmask = 1;
}
+ /* With PRT images we want to force 64 KiB block size so that the image
+ * created is consistent with the format properties returned in Vulkan
+ * independent of the image. */
+ if (sin.flags.prt) {
+ sin.forbiddenBlock.macroThin4KB = 1;
+ sin.forbiddenBlock.macroThick4KB = 1;
+ sin.forbiddenBlock.linear = 1;
+ }
+
if (surf->flags & RADEON_SURF_FORCE_MICRO_TILE_MODE) {
sin.forbiddenBlock.linear = 1;
@@ -2104,6 +2114,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
/* flags.texture currently refers to TC-compatible HTILE */
AddrSurfInfoIn.flags.texture = is_color_surface || surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
AddrSurfInfoIn.flags.opt4space = 1;
+ AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0;
AddrSurfInfoIn.numMipLevels = config->info.levels;
AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 017c7a624fd..43f97df1503 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -82,6 +82,7 @@ enum radeon_micro_mode
#define RADEON_SURF_NO_FMASK (1ull << 29)
#define RADEON_SURF_NO_HTILE (1ull << 30)
#define RADEON_SURF_FORCE_MICRO_TILE_MODE (1ull << 31)
+#define RADEON_SURF_PRT (1ull << 32)
struct legacy_surf_level {
uint64_t offset;
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