Mesa (master): freedreno/a2xx: add RB perfcounter 1-3

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Module: Mesa
Branch: master
Commit: 5939a64b15a8268bda4533bd94be6f1ce6abd9f1
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5939a64b15a8268bda4533bd94be6f1ce6abd9f1

Author: Joel Linn <jl at conductive.de>
Date:   Wed Nov 18 00:49:58 2020 +0100

freedreno/a2xx: add RB perfcounter 1-3

Xenos driver reads four perf counters in total.

v2: fix register names

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7666>

---

 src/freedreno/perfcntrs/fd2_perfcntr.c  | 3 +++
 src/freedreno/registers/adreno/a2xx.xml | 9 +++++++++
 2 files changed, 12 insertions(+)

diff --git a/src/freedreno/perfcntrs/fd2_perfcntr.c b/src/freedreno/perfcntrs/fd2_perfcntr.c
index 5231ddb0902..af9a514b6e6 100644
--- a/src/freedreno/perfcntrs/fd2_perfcntr.c
+++ b/src/freedreno/perfcntrs/fd2_perfcntr.c
@@ -957,6 +957,9 @@ static const struct fd_perfcntr_counter cp_counters[] = {
 
 static const struct fd_perfcntr_counter rb_counters[] = {
 	COUNTER(RB_PERFCOUNTER0_SELECT, RB_PERFCOUNTER0_LOW, RB_PERFCOUNTER0_HI),
+	COUNTER(RB_PERFCOUNTER1_SELECT, RB_PERFCOUNTER1_LOW, RB_PERFCOUNTER1_HI),
+	COUNTER(RB_PERFCOUNTER2_SELECT, RB_PERFCOUNTER2_LOW, RB_PERFCOUNTER2_HI),
+	COUNTER(RB_PERFCOUNTER3_SELECT, RB_PERFCOUNTER3_LOW, RB_PERFCOUNTER3_HI),
 };
 
 const struct fd_perfcntr_group a2xx_perfcntr_groups[] = {
diff --git a/src/freedreno/registers/adreno/a2xx.xml b/src/freedreno/registers/adreno/a2xx.xml
index b6ea7cd43a6..b95709cf84d 100644
--- a/src/freedreno/registers/adreno/a2xx.xml
+++ b/src/freedreno/registers/adreno/a2xx.xml
@@ -1691,8 +1691,17 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0x0a49" name="MH_PERFCOUNTER0_HI"/>
 	<reg32 offset="0x0a4d" name="MH_PERFCOUNTER1_HI"/>
 	<reg32 offset="0x0f04" name="RB_PERFCOUNTER0_SELECT"/>
+	<reg32 offset="0x0f05" name="RB_PERFCOUNTER1_SELECT"/>
+	<reg32 offset="0x0f06" name="RB_PERFCOUNTER2_SELECT"/>
+	<reg32 offset="0x0f07" name="RB_PERFCOUNTER3_SELECT"/>
 	<reg32 offset="0x0f08" name="RB_PERFCOUNTER0_LOW"/>
 	<reg32 offset="0x0f09" name="RB_PERFCOUNTER0_HI"/>
+	<reg32 offset="0x0f0a" name="RB_PERFCOUNTER1_LOW"/>
+	<reg32 offset="0x0f0b" name="RB_PERFCOUNTER1_HI"/>
+	<reg32 offset="0x0f0c" name="RB_PERFCOUNTER2_LOW"/>
+	<reg32 offset="0x0f0d" name="RB_PERFCOUNTER2_HI"/>
+	<reg32 offset="0x0f0e" name="RB_PERFCOUNTER3_LOW"/>
+	<reg32 offset="0x0f0f" name="RB_PERFCOUNTER3_HI"/>
 </domain>
 
 <domain name="A2XX_SQ_TEX" width="32">