Mesa (master): radv: enable TC-compat HTILE with D32S8 and MSAA on GFX9+

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Module: Mesa
Branch: master
Commit: cc5b6a0e897c6a1946e340c3f0b62e5ca47796f1
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc5b6a0e897c6a1946e340c3f0b62e5ca47796f1

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Mon Jan 18 16:02:56 2021 +0100

radv: enable TC-compat HTILE with D32S8 and MSAA on GFX9+

Only GFX8 has some depth/stencil resolve failures.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8562>

---

 src/amd/vulkan/radv_image.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 068dac8d714..5d3d0266e91 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -96,7 +96,8 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device,
 	/* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
 	 * tests - disable for now.
 	 */
-	if (pCreateInfo->samples >= 2 && format == VK_FORMAT_D32_SFLOAT_S8_UINT)
+	if (device->physical_device->rad_info.chip_class < GFX9 &&
+	    pCreateInfo->samples >= 2 && format == VK_FORMAT_D32_SFLOAT_S8_UINT)
 		return false;
 
 	/* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only