Mesa (main): iris: Reduce SSBO alignment requirements from 64B to 4B

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 96d8e48ed5114755e3237cdcecaccd00c9717c9e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=96d8e48ed5114755e3237cdcecaccd00c9717c9e

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Jul  2 12:39:49 2021 -0700

iris: Reduce SSBO alignment requirements from 64B to 4B

Back when SSBOs were first enabled in i965, we tried to work around
issues where the CPU and GPU were incoherently writing to the same
cacheline by forcing an alignment such that different sections of
data would fall in different cachelines.  This seems wrong.

On integrated GPUs with LLC, CPU and GPU writes should be coherent.
On integrated GPUs without LLC, we either enable snooping (so they
are again coherent), or we use WC maps (so the CPU cache isn't used).
Discrete GPUs always use WC maps (so the CPU cache isn't used).

This should work.  In other words, I think the increased alignment
was just working around coherency problems on atoms that have been
fixed in the intervening 6 year time period.

Untyped surface messages require 4B alignment.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5016
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11727>

---

 src/gallium/drivers/iris/iris_screen.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c
index 6c1bd636e46..e5fe4ac0315 100644
--- a/src/gallium/drivers/iris/iris_screen.c
+++ b/src/gallium/drivers/iris/iris_screen.c
@@ -300,14 +300,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
       return IRIS_MAP_BUFFER_ALIGNMENT;
    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
-      /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
-       * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
-       * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
-       * GPU and the CPU can be updating disjoint regions of the buffer
-       * simultaneously and that will break if the regions overlap the same
-       * cacheline.
-       */
-      return 64;
+      return 4;
    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
       return 1 << 27;
    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: