Mesa (main): crocus: Reduce SSBO alignment requirements from 64B to 4B.

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Module: Mesa
Branch: main
Commit: 4bf764d53d6db314591051939a2ad17093a4e6b0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bf764d53d6db314591051939a2ad17093a4e6b0

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Jul  2 12:47:38 2021 -0700

crocus: Reduce SSBO alignment requirements from 64B to 4B.

Mirroring a change in iris; see the previous commit for rationale.
One difference is that crocus does sometimes use CPU maps on Atoms
for *reads*...but writes don't go through CPU caches.  Should be OK.

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11727>

---

 src/gallium/drivers/crocus/crocus_screen.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/src/gallium/drivers/crocus/crocus_screen.c b/src/gallium/drivers/crocus/crocus_screen.c
index b722c9b54ca..b9853e6a231 100644
--- a/src/gallium/drivers/crocus/crocus_screen.c
+++ b/src/gallium/drivers/crocus/crocus_screen.c
@@ -305,14 +305,7 @@ crocus_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
       return CROCUS_MAP_BUFFER_ALIGNMENT;
    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
-      /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
-       * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
-       * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
-       * GPU and the CPU can be updating disjoint regions of the buffer
-       * simultaneously and that will break if the regions overlap the same
-       * cacheline.
-       */
-      return devinfo->ver >= 7 ? 64 : 0;
+      return devinfo->ver >= 7 ? 4 : 0;
    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
       return devinfo->ver >= 7 ? (1 << 27) : 0;
    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: